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27-09-2017, 05:07 PM

please send verilog code for baugh wooley multiplier for 8bitx8bit

jaseela123d · 28-09-2017, 09:55 AM

The Baugh Wooley multiplier is an interesting implementation of a multiplier. It produces a relatively standard cell shape to facilitate manufacturing, while maintaining good driving characteristics. Each full adder within the multiplier performs a similar number of calculations, with the diagonal ripple carrying propagating the input signal a constant and similar amount of times.

A problem encountered during the design and arrangement of the multiplier involved the arrangement of the required full summers. A single full adder circuit is naturally set to a very wide (or high) chip, which creates problems when working towards the smallest form factor and cost efficiency. We have tried a number of creative solutions to avoid this, including stacking these chips to create a more square shape. This, however, produced long connections as the signal wrapped around the output of one full adder at the input of another and introduced losses and capacitance. It was determined that a better solution was to implement the multiplier in a single linear direction through four complete aggregator stages, but only had three full adder rows to add the width to the design. This resulted in a more rectangular and flat circuit, but allowed us to drastically reduce the distance the signal had to travel between the chips, and decrease the overall complexity of the connections within the circuit.

This solution also resulted in a chip that could be easily located near the edge of an ALU, or in general, easily function as an auxiliary circuitry piece on a larger chip. A very regular shape (ie a rectangle) can be easily built around and incorporated into third party projects. Making sure that the contents inside the chip were densely packed, this chip can easily be added to more complex circuits, while wasting the minimum die space for the third.

By initially designing our chip we simulate a scheme and observe the response of the multiplier based on changes in input. The performance objectives that we want the multiplier to meet were determined by observing the switching characteristics of the theoretical multiplier (using a 25 f Farad capacitance). These values were established as the baselines for the switching behavior of the circuit. As shown in the table below, performance targets were met and exceeded.

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