To Design and Implementation of Complex number multiplier for DSP Applications

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Introduction

The Digital Signal Processing (DSP) is one of the core technologies in multimedia and communication systems. Many application systems based on DSP, especially the recent next-generation optical communication systems, require extremely fast processing of a huge amount of digital data. Most of DSP applications such as fast Fourier transform (FFT) require additions and multiplications.
Since the multipliers have a significant impact on the performance of the entire system, many high-performance algorithms and architectures have been proposed to accelerate multiplication. Various multiplication algorithms such as Booth, modified Booth, Braun, and Baugh-Wooley have been proposed.
The modified Booth algorithm reduces the number of partial products to be generated and is known as the fastest multiplication algorithm. Many researches on the multiplier architectures including array, parallel and pipelined multipliers have been pursued and the pipelining is the most widely used technique to reduce the propagation delays of digital circuits.

Introduction contd…

With complex data (A + jB) and (C + jD), j: imaginary number, complex multiplication is represented as follows.
(A + jB)(C + jD) = AC − BD + j (AD + BC)
here AC – BD and AD + BC are complex products of the real-part and the imaginary-part, respectively. The schematic diagram of a complex multiplier is shown in Fig, where four multipliers and two adders are required. In this study, we design a complex multiplier based on this type.
A description will be given about partial product generation and compression operation to explain the structure.

Advantages

Reducing the number of multiplication and addition because
of that:
Reduce area
Reduce Power
More speed
No data loss