The Verilog Language FULL REPORT
#1


The Verilog Language
 Originally a modeling language for a very efficient event-driven digital logic simulator
 Later pushed into use as a specification language for logic synthesis
 Now, one of the two most commonly-used languages in digital hardware design (VHDL is the other)
 Virtually every chip (FPGA, ASIC, etc.) is designed in part using one of these two languages
 Combines structural and behavioral modeling styles
Structural Modeling
 When Verilog was first developed (1984) most logic simulators operated on netlists
 Netlist: list of gates and how they’re connected
 A natural representation of a digital logic circuit
 Not the most convenient way to express test benches
 Behavioral Modeling
 A much easier way to write testbenches
 Also good for more abstract models of circuits
• Easier to write
• Simulates faster
 More flexible
 Provides sequencing
 Verilog succeeded in part because it allowed both the model and the testbench to be described together
 How Verilog Is Used
 Virtually every ASIC is designed using either Verilog or VHDL (a similar language)
 Behavioral modeling with some structural elements
 “Synthesis subset”
• Can be translated using Synopsys’ Design Compiler or others into a netlist
• Design written in Verilog
 Simulated to death to check functionality
 Synthesized (netlist generated)
 Static timing analysis to check timing
 Two Main Components of Verilog
 Concurrent, event-triggered processes (behavioral)
• Initial and Always blocks
• Imperative code that can perform standard data manipulation tasks (assignment, if-then, case)
• Processes run until they delay for a period of time or wait for a triggering event
• Structure (Plumbing)
• Verilog program build from modules with I/O interfaces
• Modules may contain instances of other modules
• Modules contain local signals, etc.
• Module configuration is static and all run concurrently
 Two Main Data Types
 Nets represent connections between things
• Do not hold their value
• Take their value from a driver such as a gate or other module
• Cannot be assigned in an initial or always block
• Regs represent data storage
• Behave exactly like memory in a computer
• Hold their value until explicitly assigned in an initial or always block
• Never connected to something
• Can be used to model latches, flip-flops, etc., but do not correspond exactly
• Shared variables with all their attendant problems
 Discrete-event Simulation
 Basic idea: only do work when something changes
 Centered around an event queue
• Contains events labeled with the simulated time at which they are to be executed
 Basic simulation paradigm
• Execute every event for the current simulated time
• Doing this changes system state and may schedule events in the future
• When there are no events left at the current time instance, advance simulated time soonest event in the queue
 Four-valued Data
 Verilog’s nets and registers hold four-valued data
 0, 1
• Obvious
 Z
• Output of an undriven tri-state driver
• Models case where nothing is setting a wire’s value
 X
• Models when the simulator can’t decide the value
• Initial state of registers
• When a wire is being driven to 0 and 1 simultaneously
• Output of a gate with Z inputs
 Four-valued Logic
 Logical operators work on three-valued logic
 Structural Modeling
 Nets and Registers
 Wires and registers can be bits, vectors, and arrays
wire a; // Simple wire
tri [15:0] dbus; // 16-bit tristate bus
tri #(5,4,8) b; // Wire with delay
reg [-1:4] vec; // Six-bit register
trireg (small) q; // Wire stores a small charge
integer imem[0:1023]; // Array of 1024 integers
reg [31:0] dcache[0:63]; // A 32-bit memory
 Modules and Instances
 Basic structure of a Verilog module:
module mymod(output1, output2, … input1, input2);
output output1;
output [3:0] output2;
input input1;
input [2:0] input2;

endmodule
 Instantiating a Module
 Instances of
module mymod(y, a, b);
 look like
mymod mm1(y1, a1, b1); // Connect-by-position
mymod (y2, a1, b1),
(y3, a2, b2); // Instance names omitted
mymod mm2(.a(a2), .b(b2), .y(c2)); // Connect-by-name
 Gate-level Primitives
 Verilog provides the following:
and nand logical AND/NAND
or nor logical OR/NOR
xor xnor logical XOR/XNOR
buf not buffer/inverter
bufif0 notif0 Tristate with low enable
bifif1 notif1 Tristate with high enable
 Delays on Primitive Instances
Instances of primitives may include delays
buf b1(a, b); // Zero delay
buf #3 b2(c, d); // Delay of 3
buf #(4,5) b3(e, f); // Rise=4, fall=5
buf #(3:4:5) b4(g, h); // Min-typ-max
User-Defined Primitives
 Way to define gates and sequential elements using a truth table
 Often simulate faster than using expressions, collections of primitive gates, etc.
Gives more control over behavior with X inputs
 Most often used for specifying custom gate libraries
 A Carry Primitive

primitive carry(out, a, b, c);
output out;
input a, b, c;
table
00? : 0;
0?0 : 0;
?00 : 0;
11? : 1;
1?1 : 1;
?11 : 1;
endtable
endprimitive
A Sequential Primitive
Primitive dff( q, clk, data);
output q; reg q;
input clk, data;
table
// clk data q new-q
(01) 0 : ? : 0; // Latch a 0
(01) 1 : ? : 1; // Latch a 1
(0x) 1 : 1 : 1; // Hold when d and q both 1
(0x) 0 : 0 : 0; // Hold when d and q both 0
(?0) ? : ? : -; // Hold when clk falls
? (??) : ? : -; // Hold when clk stable
endtable
endprimitive


DOWNLOAD FULL REPORT
http://web.cecs.pdx.edu/~mperkows/CLASS_...erilog.ppt
Reply

Important Note..!

If you are not satisfied with above reply ,..Please

ASK HERE

So that we will collect data for you and will made reply to the request....OR try below "QUICK REPLY" box to add a reply to this page
Popular Searches: counter reversibil verilog, verilog software, iir verilog, verilog program, verilog code for microprocessor designin tamil language, stuffing bits verilog, viva plugin for verilog,

[-]
Quick Reply
Message
Type your reply to this message here.

Image Verification
Please enter the text contained within the image into the text box below it. This process is used to prevent automated spam bots.
Image Verification
(case insensitive)

Possibly Related Threads...
Thread Author Replies Views Last Post
  computer networks full report seminar topics 8 42,021 06-10-2018, 12:35 PM
Last Post: jntuworldforum
  OBJECT TRACKING AND DETECTION full report project topics 9 30,655 06-10-2018, 12:20 PM
Last Post: jntuworldforum
  imouse full report computer science technology 3 24,897 17-06-2016, 12:16 PM
Last Post: ashwiniashok
  Implementation of RSA Algorithm Using Client-Server full report seminar topics 6 26,611 10-05-2016, 12:21 PM
Last Post: dhanabhagya
  Optical Computer Full Seminar Report Download computer science crazy 46 66,339 29-04-2016, 09:16 AM
Last Post: dhanabhagya
  ethical hacking full report computer science technology 41 74,442 18-03-2016, 04:51 PM
Last Post: seminar report asees
  broadband mobile full report project topics 7 23,321 27-02-2016, 12:32 PM
Last Post: Prupleannuani
  steganography full report project report tiger 15 41,334 11-02-2016, 02:02 PM
Last Post: seminar report asees
  Digital Signature Full Seminar Report Download computer science crazy 20 43,685 16-09-2015, 02:51 PM
Last Post: seminar report asees
  Mobile Train Radio Communication ( Download Full Seminar Report ) computer science crazy 10 27,938 01-05-2015, 03:36 PM
Last Post: seminar report asees

Forum Jump: