The TIGER SHARC Processor
#1

Introduction:-

The Tiger SHARC processor is the newest and most power member of this family which incorporates many mechanisms like SIMD, VLIW and short vector memory access in a single processor. This is the first time that all these techniques have been combined in a real time processor.

The TigerSHARC DSP is an ultra high-performance static superscalar architecture that is optimized for tele-communications infrastructure and other computationally demanding applications. This unique architecture combines elements of RISC, VLIW, and standard DSP processors to provide native support for 8, 16, and 32-bit fixed, as well as floating-point data types on a single chip.
Large on-chip memory, extremely high internal and external bandwidths and dual compute blocks provide the necessary capabilities to handle a vast array of computationally demanding, large signal processing tasks


More....



The TigerSHARC Processor family offers wireless infrastructure and general purpose multiprocessing system manufacturers a balanced architecture that uses characteristics of RISC, VLIW, and DSP.



[Image: w7005.gif]






As has been demonstrated in several application spaces, most notably the 3G telecoms infrastructure equipment market, TigerSHARC is the only DSP solution containing the performance and instruction set to enable an 'all software' approach. This means a TigerSHARC-based solution is better equipped to address manufacturer's requirements for flexibility, high-performance, reduced bill of materials cost and added capacity than traditional hardware approaches that rely heavily on ASICs (application-specific integrated circuits), FPGAs (field programmable gate arrays) and/or ASSPs (application specific standard products).



Performance

Through this combination, the TigerSHARC Processor gains the unique ability to process 1, 8, 16 and 32-bit fixed-point as well as floating-point data types on a single chip. This proprietary architecture establishes it in a leading position in the critical areas of performance, integration, flexibility and scalability. Optimising throughput, not just clock speed, drives a balanced DSP architecture and with throughput as the metric, the TigerSHARC Processor is the highest performance DSP for communications infrastructure and multiprocessing applications currently available.


Native support for 8, 16, and 32 bit data types


Flexibility

While also providing high system performance it also retains the highest possible flexibility in software and hardware development - flexibility without compromise. For general purpose multiprocessing applications, TigerSHARC Processor's balanced architecture optimises system, cost, power and density.

A single TigerSHARC Processor, with its large on-chip memory, zero overhead DMA engine, large I/O throughput, and integrated multiprocessing support, has the necessary integration to be a complete node of a multiprocessing system. This enables a multiprocessor network exclusively made up of TigerSHARCs without any expensive and power consuming external memories or logic.

The latest members of the TigerSHARC family are the ADSP-TS201S, ADSP-TS202S and ADSP-TS203S. The ADSP-TS201S operates at 600 MHz with 24 Mbits and can execute 4,8 billion MACs per second while achieving high floating-point DSP performance. The ADSP-TS202S operates at 500 MHz with 12 Mbits and the ADSP-TS203S operates at 500 MHz with 4 Mbits.

The TigerSHARC Processor's parallelism capabilities allow for up to four 32-bit instructions per cycle while an enhanced communication instruction set reduces some of the mountainous signal processing functions associated with wireless down to a manageable level. The TigerSHARC also provides an unmatched level of both internal and external bandwidth that enable high computation rates and high data rate processing.

The combination of all the above mentioned features positions the TigerSHARC Processor as an excellent candidate for applications requiring extremely high throughput such as the channel decoding algorithms of wireless communications.

For more information contact Analog Data Products, a division of Avnet Kopp, 011 809 6100.
Reply

Important Note..!

If you are not satisfied with above reply ,..Please

ASK HERE

So that we will collect data for you and will made reply to the request....OR try below "QUICK REPLY" box to add a reply to this page
Popular Searches: tiger sharc dsp, preschool tiger art project, sharc band saw guides, sharc architecture pdf free download, sharc band, parleg vs britannia tiger, tiger sharc processors,

[-]
Quick Reply
Message
Type your reply to this message here.

Image Verification
Please enter the text contained within the image into the text box below it. This process is used to prevent automated spam bots.
Image Verification
(case insensitive)

Possibly Related Threads...
Thread Author Replies Views Last Post
  Design Of 2-D Filters Using A Parallel Processor Architecture (Download Full Seminar Computer Science Clay 3 3,025 18-02-2012, 10:37 AM
Last Post: seminar paper
  high speed protocol processor to boost gateway performance electronics seminars 1 2,884 13-02-2012, 01:26 PM
Last Post: seminar paper
  CRUSOE PROCESSOR seminar projects crazy 6 5,448 26-01-2012, 10:55 AM
Last Post: seminar addict
  Generic Visual Perception Processor Electrical Fan 5 8,288 23-08-2011, 10:16 AM
Last Post: smart paper boy
  Macro-Processor FULL REPORT seminar class 0 1,645 27-04-2011, 10:07 AM
Last Post: seminar class
  system unit & Processor seminar class 0 1,386 16-03-2011, 10:18 AM
Last Post: seminar class
  Quad-core Processor seminar class 0 1,567 07-03-2011, 03:51 PM
Last Post: seminar class
  Ultra-fast 1,000 Core Computer Processor Using FPGA project topics 0 1,413 30-12-2010, 10:47 PM
Last Post: project topics
  tigersharc processor full report project reporter 3 7,381 28-12-2010, 01:03 PM
Last Post: seminar surveyer
  Reduced Instruction Set Computer (RISC) processor project report helper 0 1,856 22-10-2010, 04:06 PM
Last Post: project report helper

Forum Jump: