The ARM7TDMI Datasheet

  ARM7TDMI.ppt (Size: 303 KB / Downloads: 0)
ARM(v4T) ISA Features
Predicated Instruction
Conditional Instruction
Features rarely seen on other architectures
PC can be destination of data operating instructions
Load/Store Multiple
Multiple Operating Modes
Hardwired Banked Registers in each mode
General Purpose Registers
Program Status Registers
Dual ISA
ARM ISA mode
THUMB ISA mode
ARM ISA: Predicated Instruction
Why predicated instruction?
To eliminate conditional branch in small if-then-else
Limitations?
In ARM Mnemonic, condition codes are placed after instruction mnemonic
Ex: “ADD” with condition “Equal” will be “ADDEQ”
Part 1: Summary
ARM use predicated instruction to eliminate small if-then-else
However, not every instruction needs to be predicated
Less code density
ARM make PC as legal destination of every data processing instruction
Combined with load/store multiple, context switch code can be very short
Very powerful but may lead to tricky assembly programming
Suitable for single pipeline scalar processor
Banked Register makes shorter interrupt/exception latency shorter
ARM Operating Modes
ARM7TDMI supports seven modes of operation:
User (usr): Normal ARM program execution state
Class 1: Exception caused mode change
Abort mode (abt): Entered after a data or instruction prefetch abort
Undefined (und): Entered when an undefined instruction is executed
Class 2: Interrupt caused mode change
FIQ (fiq): Support a data transfer or channel process
IRQ (irq): General-purpose interrupt handling
Class 3: Software Interrupt
Supervisor (svc): Protected mode for the operating system
System (sys): A privileged user mode for the operating system
ARM Operating Modes (Cont.)
Mode Change:
Exception: Switch to Abort or Undefined (instruction) mode
Interrupts: Switch to FIQ/IRQ mode
System Calls: Switch to Supervisor mode
How about “System mode” ?
ARM State Register Set
16+2 Addressable registers in a given mode
General Purpose Registers: R0-R12
Stack Pointer: R13
Link Register: R14
PC: R15
Total 37 Registers (Bank switched)
31 General Purpose Registers
6 Status Registers
Fixed Mapping Based on Processor Mode
Mapping 37 registers into 17 registers
Virtually every operating mode has its private:
Link Register-R14
Stack Pointer-R13
Part 2: Summary
Register Banking: Make interrupt latency shorter
Smaller set of program context to save
Increase interrupt response
Fixed “Architectural Register” to “Physical Register” Mapping based on current mode
Lack of flexibility
Fewer architectural register available
THUMB Mode
What is THUMB?
Why THUMB?
ARM/THUMB Mode Switching
Differences between ARM and THUMB Modes
Thumb Mode: What is Thumb?
大拇指
Thumb ISA: 16-bit instruction, dynamically decompressed into ARM Instruction before execution
Fewer directly accessible GPRs (Only R0-R8)
The CPU can be switched between ARM ISA mode and Thumb ISA mode dynamically
The Thumb Mode: Why Thumb?
Addresses higher code density by packing common instructions into 16-bit
Reduces bus width and activities
Datapath remain unchanged, thus still 32-bit
In an typical application, performance-sensitive code can be in ARM ISA, while other code in Thumb
Denser code, less performance impact
ARM/THUMB Mode switch
Switch to ARM ISA mode automatically on exception
Can also be switch by BX (Branch and Exchange) Instruction
Note: gcc-3.X now have support for “ARM/Thumb inter-working” (Unsupported in 2.9x)