Synthesizing Sequential Programs onto Reconfigurable Computing Systems

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Introduction
Over the past five decades, semiconductor technology experienced an
unprecedented rapid improvement. The capabilities and performance
of integrated circuits grew exponentially [87]. Many physical side
effects emerged with the continuing device scaling. Some examples
include resistance-capacitance coupling, signal integrity, in-die variation,
transistor leakage, and soft error rate


Research Objectives
The objective of this dissertation is to provide designers an automatic
design methodology to implement reconfigurable computing systems and
achieve design goals, such as high performance, small area, and short time
to market.

This Dissertation

This dissertation begins with a high-level characterization to reconfigurable
computing architectures. An introduction to typical design flows
follows this characterization. This part helps us understand the characteristics
of reconfigurable systems, and identify key challenges in synthesizing
applications onto reconfigurable computing systems.
Design tools usually parse functional specifications in high-level
language programs. Many sequential languages are available. Popular
choices are C and Matlab. This dissertation uses the C programs as the
input language because the C programming language is the one with
most support and most existing designs.



Summary
Modern configurable computing systems offer enormous computing capacities,
and continue to integrate on-chip computation and storage components.
Advanced synthesis tools are required to map large applications
to these increasingly complicated chips. More importantly, these tools
must be powerful and smart enough to conduct memory optimizations to
effectively utilize on-chip distributed block RAM modules.