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Abstract”

Fourphase codes have been widely used in radar and communication areas, but the synthesis of Four phase codes with good merit factor is a nonlinear multivariable optimization problem, which is usually difficult to tackle. To get the solution of above problem many global optimization algorithms like genetic algorithm, simulated annealing, and tunneling algorithm were reported in the literature. However, there is no guarantee to get global optimum point. In this paper, a novel and efficient VLSI architecture is proposed to design Four phase Pulse compression sequences with good Merit factor. The VLSI architecture is implemented on the Field Programmable Gate Array (FPGA) as it provides the flexibility of reconfigurability and reprogram ability. The implemented architecture overcomes the drawbacks of non guaranteed convergence of the earlier optimization algorithms. Index Terms” Pulse compression, Binary sequence, VLSI architecture, Merit Factor, Sidelobe energy, FPGA

Presented By:
K. Subba Rao2 and M. Srinivasa Rao3
1V.N.R. V.J.I.E.T /ECE Department, Hyderabad, India

I. INTRODUCTION

Pulse compression codes with low autocorrelation side lobe levels and high merit factor are useful for radar [1], channel estimation, and spread spectrum communication applications. Pulse compression can be defined as a technique that allows the radar to utilize a long pulse to achieve large radiated energy but simultaneously obtaining the range resolution of a short pulse. Theoretically, in pulse compression, the code is modulated onto the pulsed waveform during transmission. At the receiver, the code is used to combine the signal to achieve a high range resolution. Range-resolution is the ability of the radar receiver to identify near by targets. The main criterion of good pulse compression is the Merit factor and discrimination. Merit factor is used to measure whether coded signal is a good or poor. This means that a code with high Merit factor is a good code while a code with low Merit factor is a poor code.