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SOFT-CORE PROCESSOR DESIGN
INTRODUCTION
Embedded Systems are hardware and software components working together to perform a specific application. They exist in abundance in our modern society and play a vital role in our everyday lives. They can be found in places such as our automobiles, in the medical field, in industrial control systems, and in entertainment electronics to name just a few.
1.1 A soft-core processor is a microprocessor fully described in software, usually in an HDL, which can be synthesized in programmable hardware, such as FPGAs. A soft-core processor targeting FPGAs is flexible because its parameters can be changed at any time by reprogramming the device. Traditionally, systems have been built using general-purpose processors implemented as Application Specific Integrated Circuits (ASIC), placed on printed circuit boards that may have included FPGAs if flexible user logic was required. Using soft-core processors, such systems can be integrated on a single FPGA chip, assuming that the soft-core processor provides adequate performance.
1.2 The main problem with the existing soft-core processor implementations targeting FPGAs is that they provide very little detail of the implementation and choices made during the development process the methodology of soft-core processor development is investigated. Altera Nios is a 5-stage pipelined general-purpose Reduced Instruction Set Computer (RISC) soft-core processor, while UT Nios is a four-stage pipelined processor. Except for some optional components, UT Nios has the functionality equivalent to the Altera Nios and achieves the performance comparable to that of the Altera Nios.The design cycles in the FPGA design methodology are much shorter than for ASICs. Therefore, the design decisions during the UT Nios development process were guided by the feedback from the previous steps.
2. RECENT DEVELOPMENTS
FPGA has made memory resources suitable for implementation of embedded system-on-programmable chip (SoPC), where a complete system fit on a single programmable chip with the processor unit also embedded inside the FPGA.
2.1 Recent advancements in Field Programmable Gate Array (FPGA) technology have resulted in FPGA devices that support the implementation of a complete computer system on a single FPGA chip. A soft-core processor is a central component of such a system.
2.2 Hard processor core: A hard processors core has dedicated silicon on the FPGA. This allows it to operate with a core frequency and have a DMIS (Dhrystone million of instructions per second) rating similar to that of a discrete microprocessor. Dhrystone's eventual importance as an indicator of general-purpose ("integer") performance of new computers made it a target for commercial compiler writers. Various modern compiler static code analysis techniques (such as dead code elimination) make the use and design of synthetic benchmarks more difficult. A benefit of the hard core is that it exits in an environment where the surrounding peripherals can be customized for the application.
2.3 Soft processor core: A soft core processor solution is implemented entirely in the logic primitives of an FPGA (fig 1). Since soft core processor cores are provided as synthesizable hardware descriptive language (HDL), they inherently provide more design flexibility than the hard cores as the designer can modify the core interface to fit better into a specific design. Soft cores provide even greater flexibility by being configurable.
2.4 Soft processor core has the following features are:-
a) Pipelined reduced instructions set computer (RISC) architecture.
b) Harvard bus architecture, implementing separate instruction and data bus.
c) General-purpose registers (128, 256 or 512 registers).
d) Various interrupt levels (both for system services and user applications).
e) Configurable instruction and data cache.
f) Custom instruction addition to the instruction set.
g) Support for optional co-processing functionality.
3. FPGA TECHNOLOGY
FPGA devices are programmable to implement arbitrary user logic. To support this programmability, FPGA devices contain three types of resources: logic blocks, I/O blocks, and programmable interconnection.
3.1 Most FPGAs contain logic blocks that consist of a lookup table (LUT), and a flip-flop. A LUT can be programmed to implement any logic function of its inputs. A LUT with n inputs is called an n-LUT. An n-LUT is internally implemented as a set of 2-to-1 multiplexers, functioning as a 2n-to-1 multiplexer. Multiplexer inputs are programmable, while select lines are used for inputs of the implemented function.
3.2 Figure 2 shows an example of a logic block consisting of a 3-LUT, and a flip-flop. An 8-to- 1 multiplexer in a LUT is implemented using 2-to-1 multiplexers. Therefore, the propagation delay from inputs to the output is not the same for all the inputs. Input IN 1 experiences the shortest propagation delay, because the signal passes through fewer multiplexers than signals IN 2 and IN 3. Since a LUT can implement any function of its input variables, inputs to the LUTs should be mapped in such a way that the signals on a critical path pass through as few multiplexers as possible. Logic blocks also include a flip-flop to allow the plementation of sequential logic. An additional multiplexer is used to select between the LUT and the flip-flop output. Logic blocks in modern FPGAs are usually more complex than the one presented here.
3.3 Each logic block can implement only small functions of several variables. Programmable interconnection, also called routing, is used to connect logic blocks into larger circuits performing the required functionality. Routing consists of wires that span one or more logic blocks. Connections between logic blocks and routing, I/O blocks and routing, and among wires themselves is programmable, which allows for the flexibility of circuit implementation. Programmability of FPGAs is commonly achieved using one of three technologies: SRAM cells, antifuses, and floating gate devices. Most devices use SRAM cells. The SRAM cells drive pass transistors, multiplexers, and tri-state buffers, which in turn control the configurable routing logic and I/O blocks. Since the content of SRAM cells is lost when the device is not powered, the configuration needs to be reloaded into the device on each power-up. This is done using a configuration device that loads the configuration stored in some form of non-volatile memory.