i would like to get details on silvaco code for nwfet

Due to their unique electronic and optical properties,
semiconductor nanowires have been the subject of extensive
research as potential building blocks for a variety of
electronic,1 photonic,2 and biomedical3 applications. Because
of the high surface area to volume ratio in nanoscale devices,
surface effects become important, and even dominant, in
their influence on electronic transport4 and optical behavior.5
While these effects can be desirable in some applications
such as highly sensitive photodetectors6 or chemical and biological
sensors,7 they may be detrimental to carrier transport
properties in nanowire field effect transistors
NWFETs.
8
In order to obtain accurate and representative measures of
transport properties in NWFETs, the capacitive effects of interface
states must be considered. While traditional
capacitance-voltage
C-V measurements can offer detailed
information concerning the presence, nature, and density of
interface trap states,9 these techniques are not readily applicable
to NWFETs due to their small gate capacitance.
Herein, we report studies on the influence of interface states
on the transport properties and parameter extraction from
top-gated InAs NWFETs carried out by steady state and
time-resolved I-V measurements.
Our efforts focus on InAs NWFETs, which are promising
for high speed nanoelectronics due to their high electron mobility
and ability to form low resistance Ohmic contacts4

1 – 10 k due to surface Fermi energy pinning in the
conduction band.10 Surface Fermi level pinning in InAs is
caused by surface reconstruction11 and by the abundance of
donor-type surface states.12 Therefore, it is expected that the
effects of surface states will be highly pronounced in this
material system. Indeed, as discussed in the following, the
InAs NWFETs show marked transient characteristics and
sweep rate dependent transconductance. By performing a
systematic characterization of the transport properties of
InAs NWFETs as well as an equivalent circuit analysis, we
are able to model and quantify their transport properties and
extract transport parameters reflective of the inherent properties
of the nanowires.
II. EXPERIMENT
InAs NWs were grown by metal-organic chemical vapor
deposition. 40 nm Au colloids were dispersed on thermally
grown SiO2 on Si
001 and the growth was performed at a
substrate temperature of 350 °C under 100 Torr chamber
pressure using trimethylindium and arsine in H2 carrier gas
at an input V/III ratio of 50 for 13– 30 min. The resulting
NWs are n type and have diameters of 60– 120 nm and
lengths of 10
m. The nanowires were then suspended in
ethanol solution and transferred onto a prepatterned grid on a
600 nm SiO2 /n+-Si
001 substrates for device fabrication
and characterization.
Source-drain contact leads with a variable separation of
0.5– 4
m were patterned by e-beam lithography and
e-beam evaporation of Ti/Al
15/ 90 nm followed by liftoff.
A 73 nm ZrO2 /Y2O3 gate dielectric
r= 12 layer was
then rf sputtered, and e-beam lithography and bilayer lift-off
were then performed to pattern the 100 nm thick Al top gate,
which was also deposited by rf sputtering. Figure 1 shows a
field-emission scanning electron microscope
FE-SEM image
of the final top-gate InAs NWFET device. The transfer
curves were measured using an HP4155 parameter analyzer
and the transient characteristics were measured using a coma
Electronic.