SECURE DIGITAL INPUT OUTPUT (SDIO)
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SDIO
SECURE DIGITAL INPUT OUTPUT

Main Features
The SD/SDIO MMC card host interface (SDIO) provides an interface between the AHB peripheral bus and MultiMediaCards (MMCs), SD memory cards, SDIO cards and CE-ATA devices.
Full compliance with MultiMediaCard System Specification Version 4.2. Card support for three different databus modes: 1-bit (default), 4-bit and 8-bit
Full compatibility with previous versions of MultiMediaCards (forward compatibility)
Full compliance with SD Memory Card Specifications Version 2.0
Full compliance with SD I/O Card Specification Version 2.0: card support for two different databus modes: 1-bit (default) and 4-bit
Features(Contd.)
Full support of the CE-ATA features (full compliance with CE-ATA digital protocol Rev1.1)
Data transfer up to 48 MHz for the 8 bit mode
Data and command output enable signals to control external bidirectional drivers.
SDIO bus topology
Communication over the bus is based on command and data transfers.
The basic transaction on the MultiMediaCard/SD/SD I/O bus is the command/response transaction. These types of bus transaction transfer their information directly within the command or response structure. In addition, some operations have a data token.
Data transfers to/from SD/SDIO memory cards are done in data blocks. Data transfers to/from MMC are done data blocks or streams. Data transfers to/from the CE-ATA Devices are done in data blocks.
SDIO functional description
The SDIO adapter block provides all functions specific to the MMC/SD/SD I/O card such as the clock generation unit, command and data transfer.
The AHB interface accesses the SDIO adapter registers, and generates interrupt and DMA request signals.
By default SDIO_D0 is used for data transfer. After initialization, the host can change the databus width.
If a MultiMediaCard is connected to the bus, SDIO_D0, SDIO_D[3:0] or SDIO_D[7:0] can be used for data transfer. MMC V3.31 or previous, supports only 1 bit of data so only SDIO_D0 can be used.
If an SD or SD I/O card is connected to the bus, data transfer can be configured by the host to use SDIO_D0 or SDIO_D[3:0]. All data lines are operating in push-pull mode.
SDIO_CMD has two operational modes:
Open-drain for initialization (only for MMCV3.31 or previous)
Push-pull for command transfer (SD/SD I/O card MMC4.2 use push-pull drivers also for initialization)
SDIO_CK is the clock to the card: one bit is transferred on both command and data lines with each clock cycle. The clock frequency can vary between 0 MHz and 20 MHz (for a MultiMediaCard V3.31), between 0 and 48 MHz for a MultiMediaCard V4.0/4.2, or between 0 and 25 MHz (for an SD/SD I/O card).
The SDIO uses two clock signals:
SDIO adapter clock (SDIOCLK = HCLK)
AHB bus clock (HCLK/2)
The SDIO adapter is a multimedia/secure digital memory card bus master that provides an interface to a multimedia card stack or to a secure digital memory card. It consists of five subunits:
Adapter register block
Control unit
Command path
Data path
Data FIFO
Adapter register block
The adapter register block contains all system registers. This block also generates the signals that clear the static flags in the multimedia card. The clear signals are generated when 1 is written into the corresponding bit location in the SDIO Clear register.
Control Unit
The control unit contains the power management functions and the clock divider for the memory card clock.
There are three power phases:
power-off
power-up
power-on
It consists of a power management subunit and a clock management subunit.
The power management subunit disables the card bus output signals during the power-off and power-up phases.
The clock management subunit generates and controls the SDIO_CK signal. The SDIO_CK output can use either the clock divide or the clock bypass mode.
The clock output is inactive:
after reset
during the power-off or power-up phases
if the power saving mode is enabled and the card bus is in the Idle state
Command path
The command path unit sends commands to and receives responses from the cards.
Command path state machine (CPSM)
When the command register is written to and the enable bit is set, command transfer starts. When the command has been sent, the command path state machine (CPSM) sets the status flags and enters the Idle state if a response is not required. If a response is required, it waits for the response
When the response is received, the received CRC code and the internally generated code are compared, and the appropriate status flags are set.
When the Wait state is entered, the command timer starts running. If the timeout is reached before the CPSM moves to the Receive state, the timeout flag is set and the Idle state is entered.
Command format
Command: a command is a token that starts an operation. Command are sent from the host either to a single card (addressed command) or to all connected cards (broadcast command are available for MMC V3.31 or previous). Commands are transferred serially on the CMD line. All commands have a fixed length of 48 bits. The general format for a command token for MultiMediaCards, SD-Memorycards and SDIO-Cards is shown in Table
CE-ATA commands are an extension of MMC commands V4.2, and so have the same format.
The command path operates in a half-duplex mode, so that commands and responses can either be sent or received. If the CPSM is not in the Send state, the SDIO_CMD output is in the Hi-Z state, as shown in Figur
Data on SDIO_CMD are synchronous with the rising edge of SDIO_CK. Table shows the command format.
Response: a response is a token that is sent from an addressed card (or synchronously from all connected cards for MMC V3.31 or previous), to the host as an answer to a previously received command. Responses are transferred serially on the CMD line.
The SDIO supports two response types. Both use CRC error checking:
48 bit short response
136 bit long response
The command register contains the command index (six bits sent to a card) and the command type. These determine whether the command requires a response, and whether the response is 48 or 136 bits long
The command path implements the status flags shown in Table
The CRC generator calculates the CRC checksum for all bits before the CRC code. This includes the start bit, transmitter bit, command index, and command argument (or card status). The CRC checksum is calculated for the first 120 bits of CID or CSD for the long response format. Note that the start bit, transmitter bit and the six reserved bits are not used in the CRC calculation.
The CRC checksum is a 7-bit value:
CRC[6:0] = Remainder [(M(x) * x7) / G(x)]
G(x) = x7 + x3 + 1
M(x) = (start bit) * x39 + ... + (last bit before CRC) * x0, or
M(x) = (start bit) * x119 + ... + (last bit before CRC) * x0
Data path
The data path subunit transfers data to and from cards.
The card databus width can be programmed using the clock control register. If the 4-bit wide bus mode is enabled, data is transferred at four bits per clock cycle over all four data signals (SDIO_D[3:0]). If the 8-bit wide bus mode is enabled, data is transferred at eight bits per clock cycle over all eight data signals (SDIO_D[7:0]). If the wide bus mode is not enabled, only one bit per clock cycle is transferred over SDIO_D0.
Depending on the transfer direction (send or receive), the data path state machine (DPSM) moves to the Wait_S or Wait_R state when it is enabled:
Send: the DPSM moves to the Wait_S state. If there is data in the transmit FIFO, the DPSM moves to the Send state, and the data path subunit starts sending data to a card.
Receive: the DPSM moves to the Wait_R state and waits for a start bit. When it receives a start bit, the DPSM moves to the Receive state, and the data path subunit starts receiving data from a card.
Data path state machine
The DPSM operates at SDIO_CK frequency. Data on the card bus signals is synchronous to the rising edge of SDIO_CK. The DPSM has six states, as shown in Figure
Card functional description
Card identification mode
Card reset
Operating voltage range validation
Card identification process
Block write
Block read
Stream access, stream write and stream read (MultiMediaCard only)
Erase: group erase and sector erase
Wide bus selection or deselection
Card status register
SD status register
SD I/O mode
Commands and responses
Protection Management
Three write protection methods for the cards are supported in the SDIO card host module:
1. internal card write protection (card responsibility)
2. mechanical write protection switch (SDIO card host module responsibility only)
3. password-protected card lock operation
Response formats
All responses are sent via the MCCMD command line SDIO_CMD. The response transmission always starts with the left bit of the bit string corresponding to the response code word. The code length depends on the response type.
A response always starts with a start bit (always 0), followed by the bit indicating the direction of transmission (card = 0). A value denoted by x in the tables below indicates a variable entry. All responses, except for the R3 response type, are protected by a CRC. Every command code word is terminated by the end bit (always 1).
There are five types of responses.
R1 (normal response command), R1b, R2 (CID, CSD register), R3 (OCR register), R4 (Fast I/O), R4b, R5 (interrupt request), R6
SDIO IO Card-specific operations
The following features are SD I/O-specific operations:
SDIO read wait operation by SDIO_D2 signalling
SDIO read wait operation by stopping the clock
SDIO suspend/resume operation (write and read suspend)
SDIO interrupts
The SDIO supports these operations only if the SDIO_DCTRL[11] bit is set, except for read suspend that does not need specific hardware implementation.
CE-ATA specific operations
The following features are CE-ATA specific operations:
sending the command completion signal disable to the CE-ATA device
receiving the command completion signal from the CE-ATA device
signaling the completion of the CE-ATA command to the CPU, using the status bit and/or interrupt.
The SDIO supports these operations only for the CE-ATA CMD61 command, that is, if SDIO_CMD[14] is set.
HW flow control
The HW flow control functionality is used to avoid FIFO underrun (TX mode) and overrun (RX mode) errors.
The behavior is to stop SDIO_CK and freeze SDIO state machines. The data transfer is stalled while the FIFO is unable to transmit or receive data. Only state machines clocked by SDIOCLK are frozen, the AHB interface is still alive. The FIFO can thus be filled or emptied even if flow control is activated.
To enable HW flow control, the SDIO_CLKCR[14] register bit must be set to 1. After reset Flow Control is disabled.
SDIO registers
The device communicates to the system via 32-bit-wide control registers accessible via AHB.
The peripheral registers have to be accessed by words (32-bit).
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