sir we want verilog code for nikhilam sutra in division method

Abstract

The performance of any processor depends entirely upon its strength, area and delay. To achieve an effective processor, its strength, area and delay should be low. The division is always considered to be heavy and is considered to be one of the most difficult operations in arithmetic and therefore VLSI architecture has high order of all the implementation and time of space algorithm in the implementation algorithm. Vedic mathematics, on the other hand, provides a new holistic approach to mathematics. Its range extends from the most concrete values ​​of numerical computation to the most intangible aspects of intelligence of mobility. In this work we have implemented an accomplished binary division architecture through the sources of Vedic Mathematics, which is the Nikhilam formula and the transparent formula. In this work, these two algorithms of the division and their application for calculation of deconvival have been discussed. Both algorithms have been implemented with better results of timely delays and with some complications. The proposed division algorithm is coded in Verilog, synthesized and imitated using Xilinx ISE Design Suite 14.2. Fake results for proposed Vedic divider circuit show a decreasing 19% delay in traditional way.