powerpoint presentation on dsp based motor control system








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sai ganesh sabat

A High Performance DSP Based System Architecture
for Motor Drive Control

Abstract
This paper presents a high speed digital signal processor (DSP) based system architecture for motor drive control. The system achieves fast speed performance by using the 50 MHz MS320C25 DSP and specialized digitalhardware to perform data acquisition and output control tasks usually performed in software. The peripheral hardware has been designed for easy interface to many types of motor drive systems, to make the system generally applicable in the motion control field. The specifications, systematic design, and realization of this general purpose controller are described. Software to support the features of the system is discussed. Experimental results using the proposed system to control a switched reluctance motor drive, both in torque mode and four quadrant speed operation, verify the speed performance of the DSP based system.
Digital controller systems are used extensively in the field of motion control. High performance digital control systems usually require the fast execution of control algorithms. Some advanced algorithms, such as for sensor-less motor drive control, require a large number of computations. As algorithms become more complex, faster digital controllers are required to
execute them within given time limitations. As some applications require motor drives to be controlled at high rotational velocities, the time which is allowable for one iteration of the control loop can be very small. Many existing controllers are designed around a microprocessor or a
microcontroller which typically runs at a moderate clock frequency and uses multiple instruction cycles for each processing step. These systems lack the ability to execute advanced algorithms fast enough for real-time control.
Recently the use of a Digital Signal Processor (DSP) as the heart of the controller has been explored. DSPs are designed for signal processing and have hardware optimizations which are directly applicable to digital control. Some of these desirable features are short instruction cycle duration, pipelining to achieve one instruction per cycle, and one cycle hardware multipliers. Several DSP based controllers have been proposed within the last several years, [1], [2], and [3]. These systems are an improvement over many existing controllers, but they depend too much on the DSP for data acquisition tasks and do not have the speed performance necessary for demanding high speed or complex algorithm control applications.
The primary design goal for the system architecture presented in the following sections is that the controller should provide enough processing power to accommodate advanced control algorithms. A specific statement of that goal is that the system be able to execute one full loop of a speed drive algorithm within 20 µs. This goal was to be achieved while retaining a feasible single processor architecture. The secondary design goal for the system is an easy and flexible motor drive interface. A specific statement of that goal is that the system should be able to achieve the first goal for any of the main types of motor drive.
The goals of the system design forced the following decisions to be made about specifications for the DSP and the input/output hardware. The instruction cycle of the DSP had to be 100 ns or lower to allow enough instructions to be executed in the 20 µs time limit. The system had to have fast memory from which to execute program code with no wait-states. At
least four consecutive analog-to-digital conversions would usually have to take place within the 20 µs time period, so the time for each conversion had to be less than 2 µs. The decoding of position encoder outputs had to be implemented in hardware, as the use of the DSP and interrupts for this task would consume a significant portion of the processing time when the motor drive ran at high rotational speeds. For flexibility, the system had to easily interface with both major types of position encoder. The creation of pulse width modulation outputs had to be implemented in hardware, since the use of the DSP for this task would consume a majority of the processing time at the desired repetition frequencies.
The design goals and specifications were met in the following high speed DSP based digital controller. The system attains good speed performance by using a fast DSP and fast data acquisition hardware. It also incorporates hardware to perform input/output tasks, position encoder decoding and pulse width modulation output generation, for which many digital controllers rely on interrupt driven software. For flexibility, the design includes more than the minimum number of analog-to-digital inputs required for phase current feedbacks. These extra analog inputs allow the system to read various types of transducers. The system also has Hardware to support both of the two main types of position encoder. Versatility of the
system is further enhanced by providing a serial communications page link to a host computer.

The main features of the system design are listed below.

• 50 MHz TMS320C25 Digital Signal Processor with 80 ns instruction cycle
• 64K by 16-bit EPROM, two banks of 16K by 16-bit static RAM
• Full function serial port with 38.4 kBaud maximum rate
• 8 channels of 10-bit ADC input with typical 1.2 µs conversion
• Decoding of three line Speed/Position/Direction input
• 8 channels of 8-bit PWM output with 49 kHz maximum frequency
• 32 bits digital input, 13 bits digital output