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On-Chip Optical Communication for Multicore Processors
Jason Miller
Carbon Research Group
MIT COMPUTER SCIENCE AND ARTIFICIAL INTELLIGENCE LAB
“Moore’s Gap”
Multicore Scaling Trends
Today
A few large cores on each chip
Diminishing returns prevent cores from getting more complex
Only option for future scaling is to add more cores
Still some shared global structures: bus, L2 caches
The Future of Multicore
Multicore Challenges
Scalability
How do we turn additional cores into additional performance?
Must accelerate single apps, not just run more apps in parallel
Efficient core-to-core communication is crucial
Architectures that grow easily with each new technology generation
Programming
Traditional parallel programming techniques are hard
Parallel machines were rare and used only by rocket scientists
Multicores are ubiquitous and must be programmable by anyone
Power
Already a first-order design constraint
More cores and more communication  more power
Previous tricks (e.g. lower Vdd) are running out of steam
Multicore Communication Today
Single shared resource
Uniform communication cost
Communication through memory
Doesn’t scale to many cores due to contention and long wires
Scalable up to about 8 cores
Multicore Communication Tomorrow
Multicore Programming Trends
Meshes and small cores solve the physical scaling challenge, but programming remains a barrier
Parallelizing applications to thousands of cores is hard
Task and data partitioning
Communication becomes critical as latencies increase
Increasing contention for distant communication
Degraded performance, higher energy
Inefficient broadcast-style communication
Major source of contention
Expensive to distribute signal electrically
Multicore Programming Trends
For high performance, communication and locality must be managed
Tasks and data must be both partitioned and placed
Analyze communication patterns to minimize latencies
Place data near the code that needs it most
Place certain code near critical resources (e.g. DRAM, I/O)
Dynamic, unpredictable communication is impossible to optimize
Orchestrating communication and locality increases programming difficulty exponentially
Improving Programmability
Observations:
A cheap broadcast communication mechanism can make programming easier
Enables convenient programming models (e.g., shared memory)
Reduces the need to carefully manage locality
On-chip optical components enable cheap, energy-efficient broadcast
ATAC Architecture
Optical Broadcast Network
Waveguide passes through every core
Multiple wavelengths (WDM) eliminates contention
Signal reaches all cores in <2ns
Same signal can be received by all cores
Optical Broadcast Network
Optical bit transmission
Core-to-core communication
ATAC Bandwidth
64 cores, 32 lines, 1 Gb/s
Transmit BW: 64 cores x 1 Gb/s x 32 lines = 2 Tb/s
Receive-Weighted BW: 2 Tb/s * 63 receivers = 126 Tb/s
Good metric for broadcast networks – reflects WDM
System Capabilities and Performance
Programming ATAC
Cores can directly communicate with any other core in one hop (<2ns)
Broadcasts require just one send
No complicated routing on network required
Cheap broadcast enables frequent global communications
Broadcast-based cache update/remote store protocol
All “subscribers” are notified when a writing core issues a store (“publish”)
Uniform communication latency simplifies scheduling
Communication-centric Computing
Summary
ATAC uses optical networks to enable multicore programming and performance scaling
ATAC encourages communication-centric architecture, which helps multicore performance and power scalability
ATAC simplifies programming with a contention-free all-to-all broadcast network
ATAC is enabled by recent advances in CMOS integration of optical components
Backup Slides
What Does the Future Look Like?
Scaling to 1000 Cores
Purely optical design scales to about 64 cores
After that, clusters of cores share optical hubs
ENet and BNet move data to/from optical hub
Dedicated, special-purpose electrical networks