Abstract
Face detection is an important aspect for biometrics,video surveillance and human computer interaction. Wepresent a multi-GPU implementation of the Viola-Jones facedetection algorithm that meets the performance of the fastestknown FPGA implementation. The GPU design offers far lowerdevelopment costs, but the FPGA implementation consumesless power. We discuss the performance programming requiredto realize our design, and describe future research directions.Keywords-Graphical Processing Unit; Face Detection; FieldProgrammable Gate Array; Acceleration.
I. INTRODUCTION
Object detection is prevalent in many applications suchas security systems and bioinformatics. Whether detecting aface, mouse or stem cell, near real-time detection is essentialfor many applications. However, typical software solutionsprovide limited frame rates of 1.78 [4] even with optimizedOpenCV [1] code that utilizes multiple processing cores.Hardware designs are able to heavily outperform softwareones by taking advantage of an application specific design.An application specific integrated circuit (ASIC) designwould without doubt achieve the highest performance. However,a custom design is expensive since even a minor changerequires that the device be re-fabricated and face detectionalgorithms require tuning for the expected type of imagebefore they can be put into production. Reconfigurabledevices, such as field programmable gate arrays (FPGAs),are more cost effective, since the designer may reconfigurethe device in software yet still realize performance thatapproaches that of an ASIC. For example, the design byCho et al. realized a rate of 16 frames per second (FPS)for VGA (640 _ 480) images [2]. However, even an FPGAdesign requires a significant engineering effort, due to thecomplexity of correctly synthesizing a register transfer level(RTL) design that meets area and timing constraints. This istrue even if a high level design language tool is used [3].In this paper, we present a more cost effective solutionbased on graphical processing units (GPUs). Our GPUdesign comes to within 5% of the frame rate of the fastestknown FPGA solution but at a significantly reduced designcost. To the best of our knowledge, this is the fastestimplementation of the Viola-Jones algorithm on a GPU. AGPU design has the advantage in that it avoids the need tomeet RTL constraints, thus, the design task entails softwaredevelopment only. Though GPU programming does requirespecialized knowledge, we deem such knowledge to be farless intrusive than that required to manage area and timingconstraints.The major contributions of this paper are:_ A implementation of the Viola-Jones Face Detectionalgorithm on GPUs._ A detailed discussion of the GPU programming designused to achieve high performance on VGA (640_480)images._ A comparison of GPU cost, implementation, and performancewith that of the best known FPGA implementation.The remainder of this paper is as follows. In Section IIwe describe prior work in accelerating facial and objectrecognition. In Section III we describe the Viola-Jones FaceDetection algorithm. We provide details of our GPU designin Section IV. In Section VI we compare the algorithm’simplementation on GPUs and FPGAs. Section VII concludesthe paper.II. RELATED WORKMuch work has been done in attempts to accelerateobject detection. Software solutions that use optimizedOpenCV implementations can obtain 1.78 FPS on VGAimage sizes [4]. An alternative is to use a hardware approachthat accelerates the calculation of the algorithm using anapplication specific design. Theocharides et al. [5] presentan ASIC architecture that heavily exploits parallelism ofthe AdaBoost face recognition technique by parallelizingaccesses of image data. They show a computation rateof 52 FPS but their image sizes are unknown. Wei etal. [6] presents a FPGA architecture that simulates onlya small section of the entire algorithm. It can achieverates up to 15 FPS for small images (120 _ 120). Nairet al. [7] developed a people detection embedded systemusing a softcore processor from Xilinx called Microblazeand achieved about 2.5 FPS for image sizes of 216 _ 288.Gao et al. [8] proposed a FPGA design focused on featureclassifier calculation. In this system, the host did the postdisplaying and necessary pre-processing; the entire designwas not implemented on a FPGA. They reported imagesizes of 256 _ 192 with a rate of 98 FPS. Cho et al.[9] proposed an architecture that performed all aspects ofthe algorithm on the FPGA, using special frame grabbersand buffers to accelerate the calculations. This hardwaredesign, even with the serial portions of the implementation,is substantially faster than conventional processor implementations,operating at 6.55 FPS for VGA images, versus0.31 FPS for single core implementations [9]. This particularimplementation computed 3 features in parallel. Most recenthighly parallelized versions can achieve up to 16.08 FPS [2]by calculating up to 8 feature classifiers in parallel. Table Icompares all the designs.


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