Can I have brief documentation or abstract for this

Abstract: With the advent of new technology in the fields
of VLSI and communication, there is also an ever growing
demand for high speed processing and low area design. It is
also a well known fact that the multiplier unit forms an
integral part of processor design. Due to this regard, high
speed multiplier architectures become the need of the day.
In this paper, we introduce a novel architecture to perform
high speed multiplication using ancient Vedic math’s
techniques. A new high speed approach utilizing 4:2
compressors and novel 7:2 compressors for addition has
also been incorporated in the same and has been explored.
Upon comparison, the compressor based multiplier
introduced in this paper, is almost two times faster than the
popular methods of multiplication. With regards to area, a
1% reduction is seen. The design and experiments were
carried out on a Xilinx Spartan 3e series of FPGA and the
timing and area of the design, on the same have been
calculated.
The speed of a processor greatly depends on its
multiplier’s performance. This in turn increases the demand
for high speed multipliers, at the same time keeping in mind
low area and moderate power consumption [2]. Over the
past few decades, several new architectures of multipliers
have been designed and explored. Multipliers based on the
Booth’s and modified Booth’s algorithm is quite popular in
modern VLSI design but come along with their own set of
disadvantages. In these algorithms, the multiplication
process, involves several intermediate operations before
arriving at the final answer. The intermediate stages include
several comparisons, additions and subtractions which
reduce the speed exponentially with the total number of bits
present in the multiplier and the multiplicand [5]. Since
speed is our major concern, utilizing such type of
architectures is not a feasible approach since it involves
several time consuming operations. In order to address the
disadvantages with respect to speed of the above mentioned
methods, and explored a new approach to multiplier design
based on ancient Vedic Mathematics. Vedic Mathematics is
an ancient and eminent approach which acts as a foundation
to solve several mathematical challenges encountered in the
current day scenario.
Vedic Mathematics existed in ancient India and was
rediscovered by a popular mathematician, Sri Bharati
Krishna Tirthaji. He bifurcated Vedic mathematics into 16
simple sutras (formulae). These Sutras deal with Arithmetic,
Algebra, Geometry, Trigonometry, Analytical Geometry
etc. The simplicity in the Vedic mathematics sutras paves
way for its application in several prominent domains of
engineering like Signal Processing, Control Engineering and
VLSI. One of the highlights of the Vedic math’s approach is
that the calculation of all the partial products required for
multiplication, are obtained well in advance, much before
the actual operations of multiplication begin. These partial
products are then added based on the Vedic math’s
algorithm to obtain the final product. This in turn leads to a
very high speed approach to perform multiplication [10]. In
this paper, we explore a novel method to further enhance the
speed of a Vedic mathematics multiplier by replacing the
existing full adders and half adders of the Vedic
mathematics based multipliers with compressors.
Compressors, in its several variants, are logic circuits which
are capable of adding more than 3 bits at a time as opposed
to a full adder and capable of performing this with a lesser
gate count and higher speed in comparison with an
equivalent full adder circuit. Section II deals with the Vedic
Multiplication Technique in detail .Section III Higher-Order
Compressors .Section IV. Section V deal with the results
and future work possible with these techniques.