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NETWORK ON CHIP (NoC)
To study and implement Network on Chip architecture on FPGA using mesh topology
Growing Chip Density
► Hundreds of Processing Elements (PEs) on a single chip
► Design Complexity
► Efficient high performance interconnect
► Scalability of communication architecture
PRESENT TECHNOLOGY
► System On Chip(SoC)
► Many computing resources on single chip
► Low power consumption
► Shared Bus interconnection for communication
DRAWBACKS OF SoC
► Vary challenging in GHz
► Long distance data transfer
► Even if wave pipelining is used synchronization breaks
► Bus topology do not scale if number of IP blocks are used
► Multilayer buses can handle only up to tens of IP blocks
► Basic errors detected but not malfunctioning of IP blocks
Solutions and Alternatives
 Regular architecture – Instead of irregular global wiring
 Point to Point Communication – Enables multiple connection, distribution of load
 Packet Based Communication
 GALS – Globally Asynchronous and Locally Synchronous
What are NoC’s?
According to Wikipedia:
 “Network-on-a-chip (NoC) is a new paradigm for System-on-Chip (SoC) design. NoC based-systems accommodate multiple asynchronous clocking that many of today's complex SoC designs use. The NoC solution brings a networking method to on-chip communications and claims roughly a threefold performance increase over conventional bus systems.”
NoC: Good news
Only point-to-point one-way wires are used, for all network sizes.
J Bandwidth scales with the network size.
J Routing decisions are distributed and the same router is re-instantiated, for all network sizes.
J NoCs increase the wires utilization (as opposed to ad-hoc p2p wires)