02-08-2011, 04:16 PM
Abstract
Multilevel inverter technology has emerged recently
as a very important alternative in the area of high-power
medium-voltage energy control. This paper presents the most
important topologies like diode-clamped inverter (neutral-point
clamped), capacitor-clamped (flying capacitor), and cascaded
multicell with separate dc sources. Emerging topologies like
asymmetric hybrid cells and soft-switched multilevel inverters are
also discussed. This paper also presents the most relevant control
and modulation methods developed for this family of converters:
multilevel sinusoidal pulsewidth modulation, multilevel selective
harmonic elimination, and space-vector modulation. Special
attention is dedicated to the latest and more relevant applications
of these converters such as laminators, conveyor belts, and unified
power-flow controllers. The need of an active front end at the
input side for those inverters supplying regenerative loads is also
discussed, and the circuit topology options are also presented.
Finally, the peripherally developing areas such as high-voltage
high-power devices and optical sensors and other opportunities
for future development are addressed.
Index Terms—Medium-voltage drives, multilevel converter,
multilevel inverter, power converters.
I. INTRODUCTION
IN RECENT YEARS, industry has begun to demand higher
power equipment, which now reaches the megawatt level.
Controlled ac drives in the megawatt range are usually connected
to the medium-voltage network. Today, it is hard to connect
a single power semiconductor switch directly to mediumvoltage
grids (2.3, 3.3, 4.16, or 6.9 kV). For these reasons, a
new family of multilevel inverters has emerged as the solution
for working with higher voltage levels [1]–[3].
Multilevel inverters include an array of power semiconductors
and capacitor voltage sources, the output of which
generate voltages with stepped waveforms. The commutation
of the switches permits the addition of the capacitor voltages,
which reach high voltage at the output, while the power
semiconductors must withstand only reduced voltages. Fig. 1
shows a schematic diagram of one phase leg of inverters with
different numbers of levels, for which the action of the power
Manuscript received December 2002 ; revised April 2002. Abstract published
on the Internet May 16, 2002. This work was supported by the Chilean Research
Fund CONICYT under Grant 1990837, Grant 1010096, and Grant 7010096 and
by the University Federico Santa María.
J. Rodríguez is with the Departamento de Electronica, Universidad Técnica
Federico Santa María, Valparaiso, Chile (e-mail: jrp[at]elo.utfsm.cl).
J.-S. Lai is with Virginia Polytechnic Institute and State University, Blacksburg,
VA 24061-0111 USA.
F. Z. Peng is with the Department of Electrical and Computer Engineering,
Michigan State University, East Lansing, MI 48826-1226 USA.
Publisher Item Identifier 10.1109/TIE.2002.801052.
Fig. 1. One phase leg of an inverter with (a) two levels, (b) three levels, and
© n levels.
semiconductors is represented by an ideal switch with several
positions. A two-level inverter generates an output voltage
with two values (levels) with respect to the negative terminal
of the capacitor [see Fig. 1(a)], while the three-level inverter
generates three voltages, and so on.
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