multilevel inverter
#1

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Diode-clamped multilevel inverter (DCMI)
 Extension of NPC
 Based on concept of using diodes to limit power devices voltage stress
Structure and basic operating principle
 Consists of series connected capacitors that divide DC bus voltage into a set of capacitor voltages
 A DCMI with nl number of levels typically comprises (nl-1) capacitors on the DC bus
 Voltage across each capacitor is VDC/(nl-1)
( nl nodes on DC bus, nl levels of output phase voltage , (2nl-1) levels of output line voltage)
 Output phase voltage can assume any voltage level by selecting any of the nodes
 DCMI is considered as a type of multiplexer that attaches the output to one of the available nodes
 Consists of main power devices in series with their respective main diodes connected in parallel and clamping diodes
 Main diodes conduct only when most upper or lower node is selected
 Although main diodes have same voltage rating as main power devices, much lower current rating is allowable
 In each phase leg, the forward voltage across each main power device is clamped by the connection of diodes between the main power devices and the nodes
General features
 For three-phase DCMI, the capacitors need to filter only the high-order harmonics of the clamping diodes currents , low-order components intrinsically cancel each other
 For DCMI employing step modulation strategy, if nl is sufficiently high, filters may not be required at all due to the significantly low harmonic content
 If each clamping diode has same voltage rating as power devices, for nl-level DCMI,
number of clamping diodes/phase = (nl-1) x (nl-2)
 Each power device block only a capacitor voltage
 Clamping diodes block reverse voltage (Dc1, Dc2, Dc3 block VDC/4, 2VDC/4 and 3VDC/4 respectively)
 Unequal conduction duty of the power devices
 DCMI with step modulation strategy have problems stabilizing/balancing capacitor voltages
 Average current flowing into corresponding inner nodes not equal to zero over one cycle
Not significant in SVC applications involving pure reactive power transfer
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#2

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