Design and Implementation of Multiple Cryptographic Algorithm Interface Circuit Based on Secure SoC
Abstract-
Based on the requirements of integrating multiple
cryptographic algorithm IP cores into secure SoC, after
analyzing the existing design of interface circuit, an interface
circuit of the multiple cryptographic algorithm IP core is
designed and implemented in this paper. Using the bridge
technology, it achieves the dynamic reconfiguration of three
cryptographic algorithm IP cores-AES, ECC and SHAI tied to
one dual-port RAM, as well as interconnection with the MCU. It
not only effectively solves the inconsistent of the operation
frequency and the interface data width of the multiple
cryptographic algorithm IP cores, but also increases interior
resource utilization rate of secure SoC and cryptographic service
speed, obtaining excellent cost performance.
Keywords-Secure SoC, Integration of multiple cryptographic
algorithm IP cores, Bridge technology, Cryptographic service,
Dynamic recorifiguration
I. INTRODUCTION
In the field of information security, the security chip based
on cryptographic technology, is able to provide cryptographic
services such as protection of integrity and confidentiality for
sensitive information of communicating parties, as well as
identity authentication and establishment of trusted
environment, etc. However, based on the eXlstmg
cryptographic algorithm IP core, how to improve the speed of
cryptographic services is still draw widespread attention, and it
is a bottleneck problem to be resolved in the engineering
design and practical application of secure chip. With growing
popularity of informatization, the demand for security of the
information service appears to be feature-rich, highly
integrated, high-speed computing and easy use. It is required
for the secure chip integrated in one single hardware platform,
through the software and hardware cooperative design fully
excavating the potential of hardware resource. It could
maximumly provides various, high-speed and convenient
friendly cryptographic service, owning uniform service
interface. It is necessary for secure chip design at present and
future to be function multifarious and highly integrated[l].
The function diversity of security chip could be realized by
software way, and could also be realized by the integration of
multiple hardware cryptographic algorithm IP cores, but the
best solution is by software and hardware cooperative design to
get excellent cost performance. Because the integration of
cryptographic algorithm IP cores gets high security level and
has better data processing speed when providing cryptographic
security service, not taking up the MCU operation resource, it
is more suitable for the practical application of secure chip than
the software method. Therefore, in the existing multifunction
secure chip design, the integration scheme of multiple
cryptographic algorithm IP cores is generally carried out to get
high computing speed and multiple functions.
II. THE ANALYSIS FOR INTERFACE DESIGN SCHEME OF
MULTIPLE CRYPTOGRAPHIC ALGORITHM IP CORES
Cryptographic service is an sequential process with many
cryptographic algorithms involved. It is one of the basic
functions of interface circuits that choosing different
cryptographic algorithm IP cores to handle the data Correctly
and sequentially. Usually, cryptographic service process is
completed by cryptographic algorithm IP core through
interface circuit, which is controlled by software. While, in the
design of the interface circuit of multiple cryptographic
algorithm IP cores, it is still necessary to solved the
inconsistent of the operation frequency and the interface data
width of each IP core.
A. The solution to inconsistent frequency between different
cryptographic algorithm IP cores
SoC design is a process as an organic whole with IP cores
reconfiguration. Normally, when realizing the IP core, the
designer would increase IP core operation frequency as far as
possible, to meet the needs of high-speed data processing.
Requiring the hardware platform and IP cores with the same
clock frequency is unrealistic. Because the operation frequency
of hardware platform often depends on the frequency of the
MCU which is a non-customized general-purpose processor.
Increasing operation frequency of MCU consistent with the
customized specified IP core will greatly raise the chip's power
consumption, resource and cost, yet hardly be helpful for the
performance of the whole SoC. When concretely realizing the
integration of the multiple cryptographic algorithm IP cores,
the operation frequency of each IP core may be different from
others and higher than that of the hardware platform. Therefore,
in order to make cryptographic algorithm IP core working with
hardware platform, the inconsistent problem between hardware
platform and these IP cores has to be solved firstly. The
solution analysis is shown as following:


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