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MOSFET
Metal Oxide Semiconductor Field Effect Transistors
 Different types of FETs
 Junction FET (JFET)
 Metal-Oxide-Semiconductor FET (MOSFET)
 Metal-Semiconductor FET (MESFET)
 Different types of FETs
 Junction FET (JFET)
 Different types of FETs
 Metal-Oxide-Semiconductor FET (MOSFET)
 Different types of FETs
 Metal-Semiconductor FET (MESFET)
Basic MOSFET (n-channel)
 The gate electrode is placed on top of a very thin insulating layer.
 There are a pair of small n-type regions just under the drain & source electrodes.
 If apply a +ve voltage to gate, will push away the ‘holes’ inside the p-type substrate and attracts the moveable electrons in the n-type regions under the source & drain electrodes.
 Increasing the +ve gate voltage pushes the p-type holes further away and enlarges the thickness of the created channel.
 As a result increases the amount of current which can go from source to drain — this is why this kind of transistor is called an enhancement mode device.
 Cross-section and circuit symbol of an n-type MOSFET.
 An n-channel MOS transistor. The gate-oxide thickness, TOX, is approximately 100 angstroms (0.01 mm). A typical transistor length, L = 2 l. The bulk may be either the substrate or a well. The diodes represent pn-junctions that must be reverse-biased
Basic MOSFET (p-channel)
 These behave in a similar way, but they pass current when a -ve gate voltage creates an effective p-type channel layer under the insulator.
 By swapping around p-type for n-type we can make pairs of transistors whose behaviour is similar except that all the signs of the voltages and currents are reversed.
 Pairs of devices like this care called complimentary pairs.
 In an n-channel MOSFET, the channel is made of n-type semiconductor, so the charges free to move along the channel are negatively charged (electrons).
 In a p-channel device the free charges which move from end-to-end are positively charged (holes).
 Note that with a n-channel device we apply a +ve gate voltage to allow source-drain current, with a p-channel device we apply a -ve gate voltage.
Structure and principle of operation
 A top view of MOSFET, where the gate length, L, and gate width, W.
 Note that L does not equal the physical dimension of the gate, but rather the distance between the source and drain regions underneath the gate.
 The overlap between the gate and the source/drain region is required to ensure that the inversion layer forms a continuous conducting path between the source and drain region.
 Typically this overlap is made as small as possible in order to minimize its parasitic capacitance.
MOSFET-Basic Structure
 I-V Characteristics of MOSFET
 Ideal Output Characteristics of MOSFET
 Types of MOSFET
 Subthreshold region
 Channel Length
 MOSFET Dimensions - Trend
 MOSFET scaling scenario
 Voltage Scaling
 Power Supply Voltage
 Threshold Voltage
 Gate Oxide Thickness
Channel Profile Evolution
 MOSFET Capacitances
 MOSFET Capacitances
 Overlap Capacitance
 Gate Resistance
 Components of Cin and Cout
New materials needed for scaling
 Since the early 1980s, the materials used for integrated MOSFET on silicon substrates have not changed greatly.
 The gate “metal” is made from highly-doped polycrystalline Si.
 The gate oxide is silicon dioxide.
 For the smallest devices, these materials will need to be replaced.
New Gate Oxide
 The capacitance per area of the gate oxide is
 Scaled MOSFETs require larger Cox, which has been achieved with smaller tox.
 Increasing K can also increase Cox, and other oxides, “high-K dielectrics” are being developed, including for example, mixtures of HfO2 and Al2O3.
 New Gate Metal
 The doped polycrystalline silicon used for gates has a very thin depletion layer, approximately 1 nm thick, which causes scaling problems for small devices.
 Others metals are being investigated for replacing the silicon gates, including tungsten and molybdenum.
Removing the substrate:
Silicon on Insulator (SOI)
 For high-frequency circuits (about 5 GHz and above), capacitive coupling to the Si substrate limits the switching frequency.
 Also, leakage into the substrate from the small devices can cause extra power dissipation.
 These problems are being avoided by making circuits on insulating substrates (either sapphire or silicon dioxide) that have a thin, approximately 100 nm layer of crystalline silicon, in which the MOSFETs are fabricated.
 SOI — silicon on insulator, refers to placing a thin layer of silicon on top of an insulator such as SiO2.
 The devices will be built on top of the thin layer of silicon.
 The basic idea of SOI is to reduced the parasitic capacitance and hence faster switching speed.
 Every time a transistor is turned on, it must first charge all of its internal (parasitic) capacitance before it can begin to conduct.
 The time it takes to charge up and discharge (turn off) the parasitic capacitance is much longer than the actual turn on and off of the transistor.
 If the parasitic capacitance can be reduced, the transistor can be switched faster — performance.
 One of the major source of parasitic capacitance is from the source and drain to substrate junctions.
 SOI can reduced the capacitance at the source and drain junctions significantly — by eliminating the depletion regions extending into the substrate.
SOI CMOS
 Silicon-on-insulator CMOS offers a 20–35% performance gain over bulk CMOS.
 As the technology moves to the 0.13-µm generation, SOI is being used by more companies, and its application is spreading to lower-end microprocessors and SRAMs.
 Some of the recent applications of SOI in high-end microprocessors and its upcoming uses in low-power, radio-frequency (rf) CMOS, embedded DRAM (EDRAM), and the integration of vertical SiGe bipolar devices on SOI are described.

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INTRODUCTION
Since the fabrication of MOSFET, the minimum channel length has been shrinking continuously. The motivation behind this decrease has been an increasing interest in high speed devices and in very large scale integrated circuits. The sustained scaling of conventional bulk device requires innovations to circumvent the barriers of fundamental physics constraining the conventional MOSFET device structure. The limits most often cited are control of the density and location of dopants providing high I on /I off ratio and finite subthreshold slope and quantum-mechanical tunneling of carriers through thin gate from drain to source and from drain to body. The channel depletion width must scale with the channel length to contain the off-state leakage I off. This leads to high doping concentration, which degrade the carrier mobility and causes junction edge leakage due to tunneling. Furthermore, the dopant profile control, in terms of depth and steepness, becomes much more difficult. The gate oxide thickness tox must also scale with the channel length to maintain gate control, proper threshold voltage VT and performance. The thinning of the gate dielectric results in gate tunneling leakage, degrading the circuit performance, power and noise margin.
Alternative device structures based on silicon-on-insulator (SOI) technology have emerged as an effective means of extending MOS scaling beyond bulk limits for mainstream high-performance or low-power applications .Partially depleted (PD) SOI was the first SOI technology introduced for high-performance microprocessor applications. The ultra-thin-body fully depleted (FD) SOI and the non-planar FinFET device structures promise to be the potential “future” technology/device choices.
In these device structures, the short-channel effect is controlled by geometry, and the off-state leakage is limited by the thin Si film. For effective suppression of the off-state leakage, the thickness of the Si film must be less than one quarter of the channel length.
The desired VT is achieved by manipulating the gate work function, such as the use of midgap material or poly-SiGe. Concurrently, material enhancements, such as the use of a) high-k gate material and b) strained Si channel for mobility and current drive improvement, have been actively pursued.
As scaling approaches multiple physical limits and as new device structures and materials are introduced, unique and new circuit design issues continue to be presented. In this article, we review the design challenges of these emerging technologies with particular emphasis on the implications and impacts of individual device scaling elements and unique device structures on the circuit design. We focus on the planar device structures, from continuous scaling of PD SOI to FD SOI, and new materials such as strained-Si channel and high-k gate dielectric.
PARTIALLY DEPLETED [PD] SOI
The PD floating-body MOSFET was the first SOI transistor generically adopted for high-performance applications, primarily due to device and processing similarities to bulk CMOS device.
The PD SOI device is largely identical to the bulk device, except for the addition of a buried oxide (“BOX”) layer. The active Si film thickness is larger than the channel depletion width, thus leaving a quasi-neutral “floating” body region underneath the channel. The V T of the device is completely decoupled from the Si film thickness, and the doping profiles can be tailored for any desired VT .
The device offers several advantages for performance/ power improvement:
1) reduced junction capacitance,
2) lower average threshold due to positive V BS during switching.
3) dynamic loading effects,in which the load device tends to be in high VT state during
switching
The performance comes at the cost of some design complexity resulting from the floating body of the device, such as
1) parasitic bipolar effect and
2) hysteretic VT variation.
Parasitic Bipolar Effect
In PDSOI an n-p-n transistor is formed with source and drain as emitter & collector respectively and body as the base. The topology typically involves an “off” transistor with the source and drain voltage set up in the “high” state (hence body voltage at“high”) When the source is subsequently pulled down, large overdrive is developed across the body-source junction, causing bipolar current to flow through the lateral parasitic bipolar transistor.This may result in circuit failure.
In SRAM bitline structures, the aggregate parasitic bipolar effect of the unselected cells on the selected bitline disturbs the read/write operations and limits the number of cells that can be attached to a bitline pair
Hysteretic VT Variation
The hysteretic VT variation due to long time constants of various
body charging/discharging mechanisms.
A commonly used gauge for hysteretic VT variation (or “history effect” as it is known in the SOI community) is the disparity in the body voltages and delays between the so-called “first switch” and “second switch” . The “first switch” refers to the case where a circuit (e.g., inverter) starts in an initial quiescent state with input “low” and then undergoes an input-rising transition. In this case, the initial dc equilibrium body potential of the switching nMOSFET is determined primarily by the balance of the back-to-back drain-to-body and body-to-source diodes. The “second switch” refers to the case where the circuit is initially in a quiescent state with input “high.” The input first falls and then rises (hence, the name “second switch”). For this case, the preswitch body voltage is determined by capacitive coupling between the drain and the body.
Input/output waveforms&nMOS body voltage for a PD SOI CMOS inverter under “first switch” & “second switch” condition is shown above
The duty cycle, slew rate, and output load also affect the hysteretic behavior of the circuits. A higher duty cycle increases hysteretic behavior due to higher switching activity causing a gain or loss of body charge and less time for the
device to return/settle to its initial equilibrium state
SCALING Si FILM: FROM PD SOI TO FD SOI
The major benefits of scaling/thinning of the Si film are: 1) reduction of junction capacitance for performance improvement, 2) better short channel roll-off, and 3) better soft error rate (SER) due to less charge generation and collection volume.
In addition, the history effect (disparity between first switch and second switch) is also reduced. The reduced junction capacitance improves delays of both the first and second switches. However, for the second switch the reduced junction capacitance reduces the capacitive coupling between the drain and the body .The resulting decrease in the pre-switch body voltage for the second switch partially offsets the performance improvement.
Unfortunately, the thinning of Si film degrades the body resistance, rendering body contacts less effective and eventually useless .Self-heating becomes more severe. Furthermore, as the film thickness is scaled below 50nm,the device may become dynamically fully depleted (or quasi-depleted);the body would become fully depleted under certain bias conditions or during certain circuit-switching transients. This necessitates a unified PD|FD device model with smooth and seamless transitions among different modes of operation. Typically, this is modeled by varying the built-in potential between the body and source junction, thus changing the amount of body charges the body-to-source junction diode can sink for a given change in the body potential .The presence of dynamic full depletion also complicates the static timing methodology. The various body voltage bounds, established based on the assumption of partial depletion need to be extended to cover this new phenomenon. Notice that dynamic depletion tends to occur first in long-channel, low VT devices. For short channel devices, the proximity of the heavily doped “halo” regions to each other increases the effective body doping, and the device is less likely to be dynamically fully depleted. In a FD_SOI device, the channel depletion layer extends through the entire Si film. This significantly reduces the floating body effect (completely eliminating the floating-body effect with ultra-thin Si films). A raised source/drain structure is typically employed to overcome the large source/drain series resistance of the thin Si film. There are two approaches to achieve the desired VT. One can use the traditional dual P+/N+ poly-silicon with a highly doped channel. This approach has several drawbacks and limitations: a) VT would be sensitive to Si film thickness variation, b) high doping degrades the carrier mobility and results in junction edge leakage due to tunneling, and c) in devices with ultra-thin body, the amount of dopant required for the desired VT can not be realistically achieved. Excessively high body doping would turn the device into a “resistor” rather than a “transistor.” Consequently, the preferred and more scalable approach is to build an “undoped” channel with the desired VT set either by the source/drain halo or by the use of midgap gate materials. The use of undoped channel a) reduces the VT sensitivity to Si film thickness variation, b) reduces dopant fluctuation effect, c) reduces transverse electric field and impurity scattering, leading to higher mobility, and d) reduces band-to-band tunneling leakage at the junction edge.