Ppt for power optimisation of LFSR for low power BIST implementation in hdl

In this letter, a low power linear feedback shift register (LFSR) is proposed for the test pattern generation (TPG) technology, while reducing power wastage during testing. The relation between the normal pattern is greater during normal mode than during the test. The proposed approach uses the concept of reducing infection in the test pattern generated by traditional LFSR. By increasing the relation between continuous bits, the infection decreases. Simulation results show that the test efficiency of interrupt controller benchmark circuits decreases by 46% in relation to the electricity consumed during the conventional LFSR.