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Microcontrollers MCS 51 Family
Introduction
Microcontroller and microprocessor
Von Neumann (Princeton) and Harvard architecture
Advantages of use of Microcontroller
Various Applications
Microcontroller and Microprocessor
Data and Program memory is on chip
Peripherals are on chip
Data handling, processing capacity is moderate
Data and Program Memory need to be interfaced externally
Peripherals need to be connected externally
Data handling and processing capacity is large
Applications Like
Appliances, Intercom, Telephone,
Security systems, Remote controls,
Video Games, Camera, Toys, TVs
Automotive and Engineering Industry
For automation and control,
Smart Instrumentation,
And So On ……………………………
MCS 51 Family by INTEL
Introduction to basic 8051 core Microcontroller
Features
8 bit Microcontroller
8 bit ALU and Registers
128 / 256 bytes on chip (Internal) RAM
4 k bytes on Chip ROM (Except 8031/8032)
On Chip Full Duplex UART
On Chip Timers
Features
Boolean Processing capability
32 bi-directional, Individually addressable I/O Lines.
64 k external Data Memory (RAM)
64 k external Program Memory (ROM)
Multiple source/vector/priority Interrupt structure
MCS 51 family variants
Various other manufacturers produce 8031 core Microcontrollers with added peripherals ADC, DAC, additional ports etc, on chip.
Some of the manufacturers are
Siemens 80C515, 80C535
Atmel 89C51/52, 89C1051
Cygnal
Dallas
Philips/Signetics
Architectural Overview
Blocks On Chip
CPU
Internal Oscillator
Interrupt Control
Serial Port
ROM and RAM
16 bit Timers
4 I/O Ports (Can function alternately as AD Bus and Control)
Pin Description
Memory Organisation
Total Memory available is in groups
.Internal and External
.Data memory and Program Memory
Internal means available ON CHIP
External means available OFF the CHIP (Externally connected to chip using Address and data pins)
PROGRAM Memory (ROM)
Program Memory
Total Capacity 64 k Bytes
Address is 16 bit (0000H to FFFFH)
Reset Vector at 0000H
Internal ROM will be accessed when Pin EA is tied to VCC
External ROM will be accessed when Pin EA is tied to GND
8031/8032 are ROMless and contains no internal ROM
Program Memory
When EA pin is tied to VCC to access Internal ROM, reset vector and INT vectors are from internal ROM.
When ROM address exceeds than the internal ROM capacity then External ROM will be accessed irrespective of the status of EA pin (Though it is tied to VCC)
Program Memory
While accessing Internal ROM External AD pins are free to be used as port lines
While accessing External ROM External AD pins are used as AD bus to place address and fetch code, and can not be used as port lines
DATA Memory (RAM)
Data Memory
Total capacity is 64 k bytes external RAM plus 128/256 bytes of internal RAM
External RAM address is 16 bit
Address Range for External Data Memory is 0000H to FFFFH
This is accessible only by indirect addressing through pointer (DPTR)
Data Memory
Internal RAM address is 8 bit
Internal Data Memory Address range is 00H to 7FH (direct addressable) and 80H to FFH (Only indirect addressable)
8031, 8051 series has 128 bytes of Internal Data Memory
8032, 8052 series has 256 bytes of Internal Data Memory
Lower 128 Bytes of Data memory contains
Lower 128 Bytes of Data memory contains
4 Register Banks of 8 registers (bytes) each. Register banks are identified as Register Bank 0 to Register Bank 3. Eight registers in each register bank are identified as R0, R1, …. ,R7. Data memory address range under Register Banks is from 00H to 1FH
Register Banks and their RAM addresses
Lower 128 Bytes of Data memory contains
The bit addressable RAM bits, in 16 bytes space (address from 20H to 2FH). This contains 128 bits. Individual bit can be addressed in bit address range 00H to 7FH. Though RAM byte address and bit address is same bit and byte is identified separately by instructions used.
Byte and Bit address example
Following are Byte addresses
MOV A, 20H ;20H is byte address
MOV R5, 6DH ;6DH is byte address
Following are bit addresses
MOV C, 20H ;20H is bit address*
CLR 40H ;40H is bit address*
(* because instructions are bit handling instructions)
Defaults
Default register bank in use is Register Bank 0 (00H to 07H)
Register bank can be changed by modifying RS1:RS0 (PSW4SW3) bits in PSW
Default Stack Pointer is 07H
Stack builds up from 08H towards 7FH.
Program Status Word
Special Function Registers (SFR)
The SFRs are control registers that control on chip peripherals.
The Address range is 80H to FFH
These registers can only be accessed by direct addressing
Some of the SFRs contain bits those are bit addressable.
Bit addresses are in the range 80H to FFH
SFRs
An Accumulator (A Register), B register and PSW are also part of SFRs.