LEON SPARC V8 Processor


  V8 Processor.ppt (Size: 120 KB / Downloads: 1)
Features

Implements a 32-bit SPARC V8 processor.
Separate instruction and data caches, hardware multiplier and divider, interrupt controller
Debug Support Unit (DSU) with trace buffer, two 24-bit timers, two UARTs
16-bit I/O port, flexible memory controller, Ethernet MAC ,PCI interface.
New modules can easily be added using the on-chip AMBA AHB/APB buses.

Integer Unit

5 stage pipelined
configurable number of Register Windows (2 - 32). Default setting of 8.
Up to four watchpoint registers configured.
Aids Software Debugging
Can cause a trap on an arbitrary instruction or data address range.
If DSU is enabled, the watchpoints can be used to enter debug mode.

Configuration using Device.vhd

Provides more configuration options than graphical
Configure AHB Master/Slave address space
PCI bus address space options
Memory Controller additional Configurations
Presently Graphical Configuration for LEON-MP not available.

Adding a Master to AHB


Each master (except the processors) is accompanied by a slave interface for configuring the module registers.
The extra available slots in ahbmi and ahbmo signals can be used to add the new master interface. The number of masters is given by MASTERS variable. The slave part can be added as previously given.
Interrupts can be added to the corresponding processor interrupt table in the file mcore.vhd. Interrupts number 12-14 are free and can be used.