07-03-2015, 08:16 PM
As I have seminar on coming week I need reference material for preparation
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radix 2 modified booth algorithm ppt
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As I have seminar on coming week I need reference material for preparation
10-03-2017, 11:50 AM
A new multiplier and accumulator (MAC) architecture for high-speed arithmetic. By combining multiplication with accumulation and the creation of a hybrid type of carry save adder (CSA), performance has been improved. Since the accumulator having the largest MAC delay was merged into CSA, the overall performance was high. The proposed CSA tree uses the radix-2-based Booth algorithm based on the complement of 1 (MBA) and has the modified matrix for the sign extension in order to increase the bit density of the operands. The CSA propagates to the least significant bits of the partial products and generates the least significant bits in advance to decrease the number of input bits of the final adder.
In addition, the proposed MAC accumulates the intermediate results in the sum and transport bit type instead of the final adder output, which allowed to optimize the channelization scheme to improve performance. The proposed architecture was synthesized with 250, 180 and 130 / xm, and a standard CMOS library of 90 nm. Based on the theoretical and experimental estimation, we analyze the results such as the amount of hardware resources, the delay, and the pipeline scheme. We use the Sakurai alpha power law for delay modeling. The proposed MAC showed superior properties to the standard design in many ways and operating twice as much as previous research on the similar clock frequency. We are experts in the field of high signal processing.
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