Abstract
Aiming low power dissipation during testing, in this paper we present a methodology for deriving
a novel BIST scheme for Modified Booth Multipliers. Reduction of the power dissipation is
achieved by: (a) introducing a suitable Test Pattern Generator (TPG) built of a 4-bit binary and
a 4-bit Gray counter, (b) properly assigning the TPG outputs to the multiplier inputs and ©
significantly reducing the test set length. The achieved reduction of the total power dissipation is
from 44.1% to 54.9%, the average reduction per test vector is from 21.4% to 36.5% while the
reduction of the peaks is from 15.8% to 34.3%, depending on the implementation of the basic
cells and the size of the MBM. The test application time is also reduced by 28.9% while the
introduced BIST scheme implementation overhead is very small.
1. Introduction
The ever-increasing trend towards denser and faster ICs has resulted in embedded logic blocks
with low controllability and observability that need to be tested at speed in order for the whole
chip to become a viable product. BIST structures are well suited for testing such blocks, since
they can cut down the cost of testing by eliminating the need of external testing for every
embedded logic block as well as apply the test vectors at speed.
The main objectives of BIST designers have traditionally been high fault coverage, small area
overhead and small application time. While these objectives still remain important, a new BIST
design objective, namely low power dissipation during test application, has recently emerged [ 1 -
5], and is expected to become one of the major objectives in the near future [6].
The power dissipated during test application is an important factor because of :
a) Cost issues. Consumer electronic products typically require a plastic package which imposes
a strong limit on the energy dissipated. Excessive dissipation during testing may also prevent
periodic testing of battery operated systems that use an on-line testing strategy.
b) Reliability issues. Although there is a significant correlation between consecutive vectors
applied to a circuit during its normal operation, the correlation between consecutive test
vectors is significantly lower. Therefore the switching activity in the circuit can be
significantly higher during testing than that during its normal operation [2]. The latter may
cause a circuit under test to be permanently damaged due to excessive heat dissipation or give
rise to metal migration (electromigration) that causes the erosion of conductors and leads to
subsequent failure of circuits [7].
c) Technology related issues. The multi-chip module (MCM) technology which is becoming
highly popular requires sophisticated probing to bare dies for fully testing them [8]. Absence
of packaging of these bare dies precludes the traditional heat removal techniques. In such
cases, power dissipated during testing can adversely affect the overall yield, increasing the
production cost.
A more detailed presentation of the motivations for low power dissipation during test application
can be found in [9].
In [9] a modified PODEM was presented which derives a test set with reduced switching
activity between consecutive test vectors, aiming the reduction of power dissipation during
testing. A BIST technique for reducing switching activity has been presented in [2], based on the
use of two LFSR TPGs operating at different speeds. [3] describes a method for synthesizing a
counter in order to reproduce on chip a set of pre-computed test patterns, derived for hard to
detect faults, so that the total heat dissipation is minimized. However, a test set targeting the hard
to detect faults of a circuit C has some characteristics not available to a test set targeting all faults
of C. In a BIST scheme some vectors generated by the TPG circuit are not useful for testing
purposes. A technique that inhibits such consecutive test vectors, by the use of a three state buffer
and the associated control logic, for LFSR TPGs was proposed in [5]. The drawbacks of this
method are that it fails to reduce test application time and suffers from high implementation cost.
The above mentioned techniques try to solve the general problem. However there are cases that
exploiting the inherent properties of a class of circuits a more efficient low power BIST scheme
can be obtained. Such a circuit is the multiplier. Multipliers are met in almost all contemporary
general and special purpose processors. An effective low power BIST scheme for Carry Save
Array Multipliers has been proposed in [4].
To the best of our knowledge no BIST scheme for Modified Booth Multipliers (MBMs)
targeting also low power dissipation during test application has been proposed in the open
literature. In this paper we address this problem by introducing a novel BIST scheme for MBMs
with sign generate. We consider MBMs with the final stage implemented both as: (a) a ripple
carry adder and (b) a group carry look ahead adder with ripple carry between groups. The
notation RC-MBMs and CL-MBMs for cases (a) and (b) will be used respectively. For the RCMBMs
the cell fault model [10] is used. The cell fault model is also used for all other modules of
the CL-MBMs except the carry look ahead adder where single stuck at faults are considered.
The rest of the paper is organized as follows: Preliminaries with respect to MBM and low
power are given respectively in Sections 2.1 and 2.2. The assignment of the TPG outputs to the
multiplier inputs is addressed in Section 3. In Section 4 we introduce a new TPG. In the same
Section, we also discuss the power dissipation characteristics of the proposed BIST scheme.
2. Preliminaries
2.1. MBM and Built – In Self Testing
Array multipliers implementing the modified Booth algorithm with 2-bit recoding feature
regularity, short execution time and small area compared to other implementations of multipliers
for signed multiplication [11]. We consider nxn MBMs (n=2k), with sign generate. A nxn MBM
is a combinational circuit with inputs a0a1...an-1, b0b1...bn-1 and outputs p0p1...p2n-1. Figure 1
presents the 8 x 8 MBM. An nxn MBM is composed by : i) r-cells, ii) ps-cells, iii) l_ps-cells (the
leftmost cell in a ps-cell row), iv) r_ps-cells (the rightmost cell in a ps-cell row) v) full adders, vi)
half adders, vii) 2-input OR gates and viii) the final result 2n-bit forming adder.


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