[attachment=15366]
Want to safely test RTR designs
Traditional simulators lack RTR support
Provide more flexibility than traditional simulators
“Black box” nature of the configuration bitstream
Design to bitstream translation is error prone
Did we get what we wanted?
A Java API to configure Xilinx FPGA bitstream
Provides complete design control
Routing
CLB configuration
Supports run-time reconfiguration
Allows for tools to be built upon it
Example low-level configuration call:
jBits.Set(row, col, S1F1.S1F1, S1F1.SINGLE_EAST0)
Java based simulator for Virtex devices
Models the FPGA hardware
Interconnected flip-flops and 4-input LUTs
Determines state information of Virtex FPGA
Allows “safe” validation of designs
Supports simulation of RTR designs
No mechanism for generating external I/O
The problem:
- How do we do test bench design?
Manage I/O in a separate process
SimulatorClient connects to VirtexDS server
Internal FPGA states travel over TCP/IP connection
Signals are probed and stimulated through JBits Pin resources
Example JBits Pin declaration:
Pin reg_pin = new Pin(pin.CLB, 4, 9, CenterWires.S0_XQ);
Pins are read using readPinValue (Pin)
Vectors are read using readVector(Pin[] IOPins)
Pins are written using setPinValue(Pin, int)
Vectors are written using writeVector(int val, Pin[] IOPins)
Method waitForStep() waits for simulator clock to be stepped
Models extend SimulatorClient class
Devices are modeled using behavioral Java code
Examples:
Limited only by the resources available to the “host” machine
Generic model operation:
public class RAMClient extends SimulatorClient {
/* class member fields */
private int[] RAMContents; /* array storing memory values */
private Pin[] addrPins; /* RAM address pins */
private Pin[] dataPins; /* RAM data I/O pins */
private Pin RWPin; /* RAM read/write pin */
private Pin CEPin; /* RAM chip enable pin */

/**
* Creates an instance of the RAMClient
*
* @param _addrPins - collection of RAM addr pins
* @param _dataPins - collection of RAM data pins
* @param _RWPin - RAM read/write pin
* @param _CEPin - RAM chip enable pin
* @param _RAMContents - RAM memory values
*
*/
public RAMClient(Pin[] _addrPins, Pin[] _dataPins, Pin _RWPin, Pin _CEPin,
int[] _RAMContents) {
Advantages
Java language easily models design
Allows hardware level simulation involving proto type hardware components
Supports RTR, unlike traditional VHDL simulators
Testbench can be designed for any Virtex bitstream
Design tool is irrelevant
Disadvantages
Only supports Virtex devices
No way to view asynchronous events
Only one device simulator can be open at a time
Very “low-level”…
Future Work
Only 1 VirtexDS can be open at a time
Allow direct access to VirtexDS event queues, rather than with a TCP/IP connection.
Allow primitives to generate events on external models. This would allow for better timing models.
Communication between external modules
Add asynchronous event support
Use JBits User Constraints File Parser to automatically obtain Pin locations
Conclusions
Provides a method to model external hardware
Allows bitstream level debugging with VirtexDS
Which means that it supports RTR
More flexible than VHDL testbenches
Graphical model representations can be designed to complement the BoardScope graphical debugger.