HAMMING CODE GENERATION AND ERROR DETECTING AND CORRECTING

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INTRODUCTION:

In this lab we will review the steps to create and compile a project on programmable logic using ISE and we will introduce the required steps to download the project into a chip. The programmable device you are you going to use is the Coolrunner CPLD. In front of you is a black plastic board with two circuit boards on it. There should be labels. One should say FPGA and the other CPLD. We are going to use the CPLD board today. We are using a Cool runner XPLA CPLD mounted on a Digilent demo board like the one in the picture above.


ABOUT VHDL:

VHDL is an acronym for very high speed ic hardware description language. The VHSIC hardware description language is an industry standard language used to describe hardware from the abstract to the concrete level. VHDL resulted from work done in the ‘70s and early ‘80s by the U.S. department of defence. Its roots are in the ADA language, as will be seen by the over all structure of the VHDL as well as other VHDL statements


Describe the design in VHDL code:

Prior to this a design methodology should be used to describe the system. The most common of these are:

• Top-down : In top-down, the main functional blocks are first defined, where each block has its defined inputs and outputs and is performing a specific function. Then a description of lower levels follows.

•Bottom-up : In this case first the individual blocks are defined and designed and then they are brought together to form the overall design.


Synthesis tools in VHDL:

Allow designers to design logic circuits by creating design descriptions without necessarily having to perform Boolean algebra or create
technology- specific, optimized functions.


Optimization process

It is the process of minimizing the circuitry by means of reducing the sum of product terms. However, the process is multi-objective and dependent on the expression being realized and the device used in implementation.