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INITIALIZATION BASED TEST PATTERN GENERATION FOR ASYNCHRONOUS CIRCUIS

1.0 INTRODUCTION
An Asynchronous Circuit is a circuit in which the parts are largely autonomous. The circuit is not governed by a clock circuit or global clock signal, but instead needs to wait only for the signals that indicate the completion of the instructions and operations. The asynchronous circuits provides a promising technology for low-power, high performance, low emission and highly modular digital circuits [6].
The design of asynchronous circuit is currently receiving significant attention, partly because of its ability to successfully tackle many of the problems present in deep sub-micrometer technologies. It is also essential for building large systems on chip using the well-established globally asynchronous locally synchronous methodology. However, testing of asynchronous circuits has not reached a level of maturity that allows low overhead high fault coverage solutions [5].
The most existing asynchronous testing methods have shortcomings such as assuming weak fault models, ignoring faults inside large components, incurring large area overhead and being applicable only to specific design styles or tools. The method which is general and can work with any Asynchronous design style is a novel “Automatic Test Pattern Generation” (ATPG) [1], [5].
The main idea is to use a standard ATPG algorithm, PODEM to be specific, for finding test vectors that excite faults and propagate their effects. In contrast with much of previous work on asynchronous circuit testing, only simple logic gates are used, so faults inside state-holding components, such as C-elements (CEs), are considered.
A complete three-step ATPG flow has been developed which gives an asynchronous net list, output test sequences. The first step breaks global feedback loops using the method of Cheng and Agrawal that is slightly modified to work with asynchronous circuits. The second step detects local feedback loops and extracts some essential information from the circuit. The third step combines PODEM with our novel state initialization method to generate the test patterns.
The proposed method targets mainly (quasi-) delay insensitive (DI) circuits with inherent data completion but is universally applicable. Although computationally intensive, it is capable of providing tests for circuits that are much larger circuits. In asynchronous data path circuits with no redundant faults, the stuck-at fault coverage achieved is of the order of 99%. The test length can be further compressed by approximately a quarter without any loss in fault coverage. The method also works well with control circuits; although there are a few examples with low fault coverage where the only possible test patterns cause logic hazards in these circuits.
In control circuits, the global loops are somewhat more common where they are used to build finite-state machines, but overall, they are a small fraction of the total number of feedback loops in a system. With global loops already broken by scan latches, local feedback loops are considered as pseudo-primary inputs (PIs) for TPG. Once a test pattern is found, CEs have to be initialized to the values assigned to their corresponding pseudo-PIs by PODEM.
Therefore, the main contribution towards the “Initialization-Based Test Pattern Generation for Asynchronous circuits” is an efficient method for finding short input-vector sequences that can set CEs to the required values. The sequences must be hazard/race free for both the good and faulty circuits