20-05-2011, 08:15 AM
Improved Design of High-Performance Parallel Decimal Multipliers
The efficient implementations of parallel decimal multipliers is demanded by the new generation of high-performance decimal floating-point units (DFUs). The architectures of two parallel decimal multipliers is described in this chapter. signed-digit radix-10 or radix-5 recodings of the multiplier and a simplified set of multiplicand multiples is used to perform the parallel generation of partial products. The partial products are then reduced in a tree structure based on a decimal multioperand carry-save addition algorithm which makes use of unconventional non BCD decimal coded number systems. optimized digit recoders for the generation of 2n-tuples, decimal carry-save adders (CSAs) and carry free adders are the new improvements which are used to reduce the latency. The software DFP (decimal floating point )implementations are about 10 times slower than the hardware DFPs thought they meet the precision requirements. The decimal floating point operation is very frequent one in the modern high performance computers but they lack performance. The decimal multiplication is more difficult to implement than the binary floating point multiplication because:-complexity in the generation of multiplicand multiples
-inefficiency of representing decimal values in systems based on binary signals
Owing to the inefficiency of the parallel decimal multipliers, most of the commercial implementations of the decimal multipliers are sequential in nature. The iterative algorithms for decimal integer multiplication are used in these and hence are inefficient. tree-like (parallel) structures are used to speed up multi operand BCD addition. The combinational decimal fixed-point architectures is described in this article.
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