Introduction
The communications infrastructure that has become so much a part of daily life is expanding at
an exponential rate. Figure 1 illustrates the diverse range of communication technologies used
virtually on a daily basis: wireless cellular (high and low mobility users), satellite, and microwave
links. To meet consumer, business and life-style demands infrastructure suppliers must build
sophisticated systems that no longer simply support telephony services, but provide voice, high
bit-rate data, video, image and multimedia capability. These systems must also interact with
sophisticated systems like the internet. Human nature dictates that there will be a range of
communication standards that evolve. There will also be a range of user terminals that need to be
connected to this rich communications tapestry, including cell phones, video phones, satellite
phones, PDAs, portable computers and other nomadic computing devices. To flourish and
succeed in this dynamic environment equipment suppliers must build highly flexible systems that
operate across multiple wireless and wired network standards. They must be able to rapidly
adopt new business models as they evolve, and they must be able to incorporate new signal
processing techniques that allow increased network capacity, increased coverage, increased
quality of service, or a combination of the above. The answer to the diverse range of
requirements is the software defined radio.
Software defined radios (SDR) are highly configurable hardware platforms that provide the
technology for realizing the rapidly expanding third (and future) generation digital wireless
communication infrastructure. Many sophisticated signal processing tasks are performed in a
SDR, including advanced compression algorithms, power control, channel estimation,
equalization, forward error control, adaptive antennas, rake processing in a WCDMA (wideband
code division multiple access) system and protocol management. While there are a plethora of
silicon alternatives available for implementing the various functions in a SDR, field programmable
gate arrays (FPGAs) are an attractive option for many of these tasks for reasons of performance,
power consumption and configurability. This tutorial will describe how many of the functions
required in a software radio system can be realized in an FPGA. Topics discussed will include
adaptive channel equalizers and channelization functions. Amongst the more arithmetically
demanding tasks performed in a high data rate wireless system is channel equalization. We
describe and examine the FPGA mechanization of equalizers for QAM (quadrature amplitude
modulation) systems. The implementation of the equalizer using state-of-the-art FPGA
semiconductor technology, that provides a high-performance multiplier fabric, is discussed. The
design and simulation of equalizers that employ fixed-point arithmetic is described.
Satellite
High-tier Regional Area
Low-tier
High Mobility Low Mobility
Wide Area
Local Area
Figure 1: Future generation communication environments will need to support a multitude of
modes of operation and air interfaces.
2 FPGA Architecture
FPGAs have experienced extensive architectural innovations in the past several years. Advanced
process technology has enabled the development of high density1 devices that are extremely well
suited to the needs to high-performance real-time signal processing. The architecture of the Xilinx
VirtexÔ-II is shown in Figure 2. The device is organized as an array of logic elements and
programmable routing resources used to provide the connectivity between the logic elements,
FPGA I/O pins and other resources such as on-chip memory, delay lock loops and embedded
hardware multipliers
Figure 2: Virtex-II FPGA architecture. This FPGA family provides an array of 18x18-bit precision
multipliers for addressing advanced sign al processing applications.
1 State-of-the-art FPGAs like the Xilinx Virtex family provide devices with approximately quarter of
a billion transistors and in excess of 3 million system gates.
The FPGA resources of particular interest to the signal processing engineer are configurable
dual-port block memories, distributed memory and the multiplier array [10]. The multiplier array is
composed of 18x18-bit precision mutlipliers that can operate in combinatorial mode (140 MHz) or
they can be pipelined (1-stage) to support clock frequencies up to 250 MHz. The smallest Virtex-II
device provides a modest 4 multipliers while the largest supplies an impressive 192 multipliers.
3 Software Radios
The ever-increasing demand for mobile and portable communication requires high-performance
systems employing advanced signal processing techniques to allow operation as close as
possible to the Shannon information theoretic bound [13]. However, not only must these systems
provide exceptional performance, but due to market and fiscal pressures, they must be flexible
enough to allow the rapid tracking of evolving and fluid standards. Software defined radios are
emerging as a viable solution for meeting the conflicting demands in this arena. SDRs support
multimode and multiband modes of operation to allow service providers an economic means of
future-proofing these increasingly complex and costly systems.
The use of the term software may give the impression that the radio is realized entirely on a
processor-based platform. This is not the case. The essence of the SDR is flexibility. The
flexibility to support multiple air-interfaces and to have the provision to easily and rapidly change
the nature of the signal processing chain that is the kernel technology in these systems. DSP
microprocessors, even with advanced architectural extensions (very long instruction word (VLIW),
super-scalar, etc.) do not satisfy the arithmetic or I/O requirements of a modern communication
signal processing engine. Advanced field programmable gate array technology offers a solution.
FPGA-based signal processors provide high-performance, while at the same time maintaining
flexibility through static RAM configurability [10]. A receive subsystem of a concept FPGA-based
base transceiver station (BTS) is shown in Figure 3. The figure also shows various feedback
loops for providing digital gain control in the digital down converters (DDCs) in addition to a
digitally controlled AGC (automatic gain control) loop. Typically this will be a low-bandwidth loop
which allows the application of novel sigma-delta modulation techniques [1] for efficiently
generating analog signals using FPGAs without the requirement of a digital-to-analog converter
(DAC).
Mixer

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