Implementation of Dynamically Reconfigurable Control Structures on a Single FPGA
#1

Implementation of Dynamically Reconfigurable Control Structures on a
Single FPGA Platform
Keywords

«Direct torque control (DTC) », «Direct field oriented control (DFOC) ».
Abstract
More than one control schemes for the motor control with the dynamic change-over between them is
termed as “dynamically reconfigurable control structures”. Such a dynamically reconfigurable control
structure for induction machine is proposed and implemented on a single FPGA platform. The
inherent feature of FPGA i.e. the parallel execution offers ease and more enabling to implement such a
multiple control structure. The content of paper emphasises on the basic arrangement of concept,
implementation, sharing the common modules between the control schemes and the space
characterization on FPGA.
1 Introduction
Today’s standard AC drives from the manufacturer come mostly with v/f control, field-oriented vector
control (FOC, most of the manufactures), or Direct Torque Control (DTC) [2]. They are implemented
on a micro controller or a DSP. The v/f control is often used for simple drive applications, but it is also
used as an intermediate step or backup during the commissioning phase towards sophisticated vector
control. Though many drive controllers provide several variants of controls as menu, on-the-fly
change-over of controls is not available as a standard feature.
The FOC or the DTC are well known for good control dynamics compared to v/f control, but during
steady state the v/f control is smoother in operation compared to them. There could be many
applications which need these kinds of control requirements together, for example few of them listed
below.
- To meet the load requirements; the load may require high torque dynamics during the acceleration
so that DTC is suitable, and later during steady state FOC, e.g., due to reasons of harmonics.
- To ensure sensorless start-up; operation of a speed sensorless induction motor control close to
zero speed is always a problem, unless it has a highly sophisticated speed estimator. However, in
many cases the requirements during the start-up phase are low. Thus, the motor can be started with
open-loop v/f control, and, when it reaches to some reasonable speed, control can be changed over
to the sensorless control (either based on DTC or FOC)
- As a fall back strategy; in case of sensor failures, closed-loop control can be switched over to
open-loop v/f control to retain operation with reduced performance.
To achieve the above requirements it is essential to accomplish an on-the fly change-over between the
controls, such a structure can be defined as dynamically reconfigurable control structure. These
structures based on the control schemes usage, can be classified as
- Reconfiguration between the high performance control schemes (e.g. FOC with variants of DTC)
- Reconfiguration between a low and a high performance control schemes (e.g. v/f with FOC or
DTC)
Especially in this paper it is tried to show the proposed feature with the combination of two high
performance control structures of induction motor drives.
The considered controls are Direct Field Oriented control (DFOC) and Pulse Width Modulated DTC
(PWM-DTC). DFOC utilises the rotor flux orientation to implement the current controller and while
the PWM-DTC is based on the feed-forward stator flux control. We have chosen the control structure
such that is one of the very challenging combinations; because controls regulate different fluxes of the
motor. At any instant of change-over in the control scheme there is always a disturbance on the flux
line, due to the difference in the stator and rotor flux magnitudes. To estimate these flux vectors a
closed-loop full-order observer with stator and rotor fluxes as state variables is implemented. This acts
as a common observer for both of the control structures.
From the implementation point of view, FPGAs suit better compared to DSPs or microcontrollers, due
to their inherent quality of parallel execution. Along with this, FPGAs will also give the flexibility in
“bit width” control (of individual module) to enhance the accuracy and sharing common modules with
ease.
The paper is organised as follows. The basic arrangement of control structures is explained with the
help of block diagram in Section 2. The implementation details; space characterisations, and dynamic
reconfigurable feature are given in Section 3. The detailed experimental results are in Section 4 and
followed by the conclusions in Section 5.

Download full report
http://wwwlea.uni-paderborn.de/fileadmin...ctures.pdf
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