16-08-2011, 02:31 PM
1. Deviation-Based LFSR Reseeding for Test-Data Compression---IEEE
2. IMPLEMENTATION OF ALGORITHMS FOR SUCCESSIVE INTERFERENCE CANCELLATION IN CDMA USING MATLAB
3. CONTENT BASED IMAGE RETRIEVAL SYSTEM USING PCA
4. A Fast Hardware Approach for Approximate, Efficient Logarithm and Antilogarithm Computations---IEEE
5. Fault Secure Encoder and Decoder for Memory Applications---IEEE
6. A Full-Adder-Based Methodology for the Design of Scaling Operation in Residue Number System---IEEE
7. A VLSI Progressive Coding for Wavelet-based Image Compression---IEEE
8. VLSI Design of Diminished-One Modulo n + Adder Using Circular Carry Selection---IEEE
9. Hardware implementation of Variable Precision Multiplication on FPGA---IEEE
10. IMPLEMENTATION OF WCDMA USING VHDL
11. Design and Implementation of a Field Programmable CRC Circuit Architecture---IEEE
12. THE CURVELET TRANSFORM FOR IMAGE DENOISING
13. Efficient On-Chip Crosstalk Avoidance CODEC Design---IEEE
14. IMPLEMENTATION OF BQ ALGORITHM & ARITHMETIC CODING FOR DATA COMPRESSION
15. Asynchronous Computing in Sense Amplifier-based Pass Transistor Logic---IEEE
16. Left to Right Serial Multiplier for Large Numbers on FPGA
17. FPGA Implementation of Viterbi Decoder---IEEE
18. NOISE CLEANING USING AVERAGING, MEDIAN AND ROTATING FILTERS & CONTRAST ENHANCEMENT USING GAMMA CORRECTION OF DIGITAL TRUE COLOR IMAGES
19. IMPLEMENTAION OF IMAGE RESTORATION & IMAGE ENHANCEMENT TECHNIQUES USING MATLAB
20. Power Optimization of Linear Feedback Shift Register (LFSR) for Low Power BIST---IEEE
21. Soft-Error Tolerance and Mitigation in Asynchronous Burst-Mode Circuits---IEEE
22. MORPHOLOGICAL OPERATORS FOR COLOR IMAGE PROCESSING
23. A New Low Power Test Pattern Generator Using a Variable-Length Ring Counter---IEEE
24. A Novel Multiplexer based truncated array multiplier
25. A Low-Power Low-Area Multiplier Based on Shift-and-Add Architecture---IEEE
26. Designing Efficient Online Testable Reversible Adders with New Reversible Gate---IEEE
27. Novel Area-Efficient FPGA Architectures for FIR Filtering With Symmetric Signal Extension---IEEE
28. IMPLEMENTATION OF SPATIAL AND FREQUENCY DOMAIN TECHNIQUES FOR IMAGE ENHANCEMENT
29. A Fast VLSI Design of SMS Cipher Based on Twisted BDD S-Box Architecture---IEEE
30. IMAGE WATERMARKING USING WAVELETS & DIRECTIONAL FILTER BANKS
31. Fast Enhancement of Validation Test Sets for Improving the Stuck-at Fault Coverage of RTL Circuits---IEEE
32. The Design and FPGA Implementation of GF ( ) Multiplier for Ghash---IEEE
33. IMPLEMENTATION OF HISTOGRAM EQUALIZATION TECHNIQUES
34. Superscalar Power Efficient Fast Fourier Transform FFT Architecture
35. A Generalization of a Fast RNS Conversion for a New -Modulus Base---IEEE
36. Exploiting Memory Soft Redundancy for Joint Improvement of Error Tolerance and Access Efficiency---IEEE
37. Spread Spectrum Image Watermarking with Digital Design---IEEE
38. IMPLEMENTATION OF EDGE DETECTION TECHNIQUES USING MATLAB
39. A Compact AES Encryption Core on Xilinx FPGA
40. IMAGE COMPRESSION USING BIORTHOGONAL WAVELET TRANSFORMS
41. Design of Network-on-Chip Architectures with a Genetic Algorithm-Based Technique---IEEE
