High-Speed VLSI Arithmetic Units: Adders and Multipliers


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Introduction

Digital computer arithmetic is an aspect of logic design with the objective of developing
appropriate algorithms in order to achieve an efficient utilization of the available hardware [1-4].
Given that the hardware can only perform a relatively simple and primitive set of Boolean
operations, arithmetic operations are based on a hierarchy of operations that are built upon the
simple ones. Since ultimately, speed, power and chip area are the most often used measures of
the efficiency of an algorithm, there is a strong page link between the algorithms and technology used
for its implementation.

Multiplication

Algorithm:
In microprocessors multiplication operation is performed in a variety of forms in hardware and
software depending on the cost and transistor budget allocated for this particular operation. In the
beginning stages of computer development any complex operation was usually programmed in
software or coded in the micro-code of the machine. Some limited hardware assistance was
provided. Today it is more likely to find full hardware implementation of the multiplication in
order to satisfy growing demand for speed and due to the decreasing cost of hardware [2-5]. For
simplicity, we will describe a basic multiplication algorithm which operates on positive n-bit
long integers X and Y resulting in the product P which is 2n bit long.

Conclusion

In the past, a thorough examination of the algorithms with the respect to particular technology
has only been partially done. The merit of the new technology is to be evaluated by its ability to
efficiently implement the computational algorithms. In the other words, the technology is
developed with the aim to efficiently serve the computation. The reverse path; evaluating the
merit of the algorithms should also be taken. Therefore, it is important to develop computational
structures that fit well into the execution model of the processor and are optimized for the current
technology. In such a case, optimization of the algorithms is performed globally across the
critical path of its implementation.
Ability to integrate 100 millions of transistors onto the silicon has changed our focus and the
way we think. Measuring the quality of the algorithm by the minimum number of devices used
has simply vanished from the picture. However, new concerns such as power, have entered it.