Flip Chip Packaging

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What is Flip Chip?

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Flip Chip (FC) is not a specific package (like SOIC), or even a package type (like BGA). Flip Chip describes the
method of electrically connecting the die to the package carrier. The package carrier, either substrate or leadframe,
then provides the connection from the die to the exterior of the package. In "standard" packaging, the interconnection
between the die and the carrier is made using wire. The die is attached to the carrier face up, then a wire is
bonded first to the die, then looped and bonded to the carrier. Wires are typically 1-5 mm in length, and 25-35
μm in diameter. In contrast, the interconnection between the die and carrier in flip chip packaging is made
through a conductive "bump" that is placed directly on the die surface. The bumped die is then "flipped over" and
placed face down, with the bumps connecting to the carrier directly. A bump is typically 70-100 μm high, and
90-125 μm in diameter.



Benefits of Flip Chip:
Using flip chip interconnect offers a number of possible advantages to the user:
• Reduced signal inductance - because the interconnect is MUCH shorter in length (0.1 mm vs 1-5 mm), the inductance of the signal
path is greatly reduced. This is a key factor in high speed communication and switching devices
• Reduced power/ground inductance - by using flip chip interconnect, power can be brought directly into the core of the die, rather than
having to be routed to the edges. This greatly decreases the noise of the core power, improving performance of the silicon
• Higher signal density - the entire surface of the die can be used for interconnect, rather than just the edges. This is similar to the
comparison between QFP and BGA packages. Because flip chip can connect over the surface of the die, it can support vastly larger
numbers of interconnects on the same die size
• Die shrink - for pad limited die (die where size is determined by the edge space required for bond pads), the size of the die can be
reduced, saving silicon cost
• Reduced package footprint - in some cases, the total package size can be reduced using flip chip. This can be achieved by either
reducing the die to package edge requirements, since no extra space is required for wires, or in utilizing higher density substrate
technology, which allows for reduced package pitch

Packaging Options Using Flip Chip:
Depending on the specific die and application requirements, different package level solutions are required. Thus flip chip interconnect can
be used in a wide range of package solutions, each focused on specific benefits that serve a given market. Amkor offers the widest possible
range of flip chip packaging solutions to meet the diverse needs of customers and end users. Combining their extensive manufacturing
knowledge with all types of packaging interposers and further leveraging their leadership role in flip chip interconnect technology,
Amkor continues to pursue new package solutions. This kind of focus is essential to insure that as new market needs emerge requiring
flip chip interconnect, Amkor is ready with the optimum package to meet those needs.

Amkor Technology is now offering SuperFC® packaging, the super performance flip chip solution. Flip chip interconnect utilizes array
interconnect of die to substrate as a replacement for conventional wire bonding. This allows
the entire die surface to be used for electrical connections to the substrate, exponentially
increasing the I/O per unit area vs. perimeter interconnect technologies. Implementing
process technology licensed from industry leader LSI Logic, Amkor’s SuperFC package uses
solder bump flip chip interconnect, and can route over 1000 signal traces from a single die
out to a 1.0 mm pitch BGA footprint.
SuperFC packages are assembled around state-of-the-art laminate substrates. Utilizing
multi-layer, blind and buried vias, laser drilled build-up structures, and ultra fine line/space
metallization, SuperFC has the highest routing density BGA available. Using flip chip
interconnect automatically improves package electrical performance by removing the high
inductance wires and replacing them with low inductance solder connections. By combining
flip chip with ultra advanced substrate technology, packages can be electrically tuned for
maximum electrical performance.
Wafer Bumping Technology:
Amkor has qualified volume production wafer bumping available at its Singapore, Korea, Taiwan and North Carolina facilities.
Amkor’s bumping is based on its proprietary electroplating solder technology which is considered the most advanced, robust, reliable
and high yielding process available in the marketplace. Low Alpha Eutectic, High Lead, and Lead-free are in high volume production
at all facilities. 300 mm wafer bumping production is offered in the Taiwan and Singapore facilities.


Features:
• 4-12 layer build up substrates using epoxy laminate
• Target Market - Internet Workstation Processors, High Bandwidth System Communications Devices
• Attached one or two piece heat spreader design for maximum thermal performance
• 150 μm minimum bump pitch
• Die sizes up to 26 mm
• Package sizes from 17 mm to 52.5 mm
• JEDEC MS-034 compliant, 1.0 mm pitch BGA footprint
• Package solutions up to 2400 balls