Hey pls can u provide me with a pdf or more details of this seminars. Am really interested in this topic.Pls help

Reference: http://studentbank.in/report-finfet-tech...z0qw2h1wuc

Multigate device:A multigate device or Multiple Gate Field Effect Transistor(MuGFET) refers to a MOSFET which incorporates more than one gate into a single device.

FinFETs
This term refers to a nonplanar, double-gate transistor built on an SOI substrate. based on the earlier DELTA (single-gate) transistor design.This term was was coined by University of California, Berkeley researchers . In FinFETs the conducting channel is wrapped around a thin silicon "fin", which forms the body of the device.the effective channel length of the device is determined by the dimensions of the fin. AMD, IBM, and Motorola describe their double-gate development efforts as FinFET. any fin-based, multigate transistor architecture is described generically by the term FinFET regardless of number of gates. The Taiwan Semiconductor Manufacturing Company developed a 25-nm transistor operating on just 0.7 Volt . It has a gate delay of just 0.39 picosecond.
http://eetimesstory/OEG20021210S0002

[b]FinFET technology[\b]

FinFETs are seen as the most
likely candidate for the successor of the bulk CMOS from
the 22 nm node onwards, because of its compatibility with
the current CMOS technology.digital logic, SRAM, DRAM to Flash memory have all been demonstrated in FinFET. They have superior subthreshold
performance and excellent current saturation and as a result have applications in high-gain analog applications and in RF applications.

DEVICE FABRICATION:
-Processing of tall fin-structures:
very high
etching anisotropy is required to keep the fins narrow in the etching of tall fin-structures for for the highly-scaled devices.

-MOS devices on tall fins:
They are the FinFETs built on tall and narrow fin
structures. The
standard gate-stack with thermally-grown silicon-dioxide as the gate dielectric and LPCVD polysilicon as the gate
material.

for further details, refer this links:
http://en.wikipediawiki/Multigate_device#FinFETs
and refer this pdf too:


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INTRODUCTION

Since the fabrication of MOSFET, the minimum channel length has been shrinking continuously. The motivation behind this decrease has been an increasing interest in high speed devices and in very large scale integrated circuits. The sustained scaling of conventional bulk device requires innovations to circumvent the barriers of fundamental physics constraining the conventional MOSFET device structure. The limits most often cited are control of the density and location of dopants providing high I on /I off ratio and finite subthreshold slope and quantum-mechanical tunneling of carriers through thin gate from drain to source and from drain to body. The channel depletion width must scale with the channel length to contain the off-state leakage I off. This leads to high doping concentration, which degrade the carrier mobility and causes junction edge leakage due to tunneling. Furthermore, the dopant profile control, in terms of depth and steepness, becomes much more difficult. The gate oxide thickness tox must also scale with the channel length to maintain gate control, proper threshold voltage VT and performance. The thinning of the gate dielectric results in gate tunneling leakage, degrading the circuit performance, power and noise margin.

Alternative device structures based on silicon-on-insulator (SOI) technology have emerged as an effective means of extending MOS scaling beyond bulk limits for mainstream high-performance or low-power applications .Partially depleted (PD) SOI was the first SOI technology introduced for high-performance microprocessor applications. The ultra-thin-body fully depleted (FD) SOI and the non-planar FinFET device structures promise to be the potential “future” technology/device choices.

In these device structures, the short-channel effect is controlled by geometry, and the off-state leakage is limited by the thin Si film. For effective suppression of the off-state leakage, the thickness of the Si film must be less than one quarter of the channel length.
The desired VT is achieved by manipulating the gate work function, such as the use of midgap material or poly-SiGe. Concurrently, material enhancements, such as the use of a) high-k gate material and b) strained Si channel for mobility and current drive improvement, have been actively pursued.

As scaling approaches multiple physical limits and as new device structures and materials are introduced, unique and new circuit design issues continue to be presented. In this article, we review the design challenges of these emerging technologies with particular emphasis on the implications and impacts of individual device scaling elements and unique device structures on the circuit design. We focus on the planar device structures, from continuous scaling of PD SOI to FD SOI, and new materials such as strained-Si channel and high-k gate dielectric.

PARTIALLY DEPLETED [PD] SOI

The PD floating-body MOSFET was the first SOI transistor generically adopted for high-performance applications, primarily due to device and processing similarities to bulk CMOS device.
The PD SOI device is largely identical to the bulk device, except for the addition of a buried oxide (“BOX”) layer. The active Si film thickness is larger than the channel depletion width, thus leaving a quasi-neutral “floating” body region underneath the channel. The V T of the device is completely decoupled from the Si film thickness, and the doping profiles can be tailored for any desired VT .

The device offers several advantages for performance/ power improvement:
1) reduced junction capacitance,
2) lower average threshold due to positive V BS during switching.
3) dynamic loading effects,in which the load device tends to be in high VT state during
switching
The performance comes at the cost of some design complexity resulting from the floating body of the device, such as
1) parasitic bipolar effect and
2) hysteretic VT variation.


Parasitic Bipolar Effect
In PDSOI an n-p-n transistor is formed with source and drain as emitter & collector respectively and body as the base. The topology typically involves an “off” transistor with the source and drain voltage set up in the “high” state (hence body voltage at“high”) When the source is subsequently pulled down, large overdrive is developed across the body-source junction, causing bipolar current to flow through the lateral parasitic bipolar transistor.This may result in circuit failure.

In SRAM bitline structures, the aggregate parasitic bipolar effect of the unselected cells on the selected bitline disturbs the read/write operations and limits the number of cells that can be attached to a bitline pair
Hysteretic VT Variation
The hysteretic VT variation due to long time constants of various
body charging/discharging mechanisms.
A commonly used gauge for hysteretic VT variation (or “history effect” as it is known in the SOI community) is the disparity in the body voltages and delays between the so-called “first switch” and “second switch” . The “first switch” refers to the case where a circuit (e.g., inverter) starts in an initial quiescent state with input “low” and then undergoes an input-rising transition. In this case, the initial dc equilibrium body potential of the switching nMOSFET is determined primarily by the balance of the back-to-back drain-to-body and body-to-source diodes. The “second switch” refers to the case where the circuit is initially in a quiescent state with input “high.” The input first falls and then rises (hence, the name “second switch”). For this case, the preswitch body voltage is determined by capacitive coupling between the drain and the body.

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presented by:
Venkatnarayan Hariharan

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Abstract
In this report, the basic FinFET structure is described, along with the reasons behind its introduction. The fabrication steps are briefly discussed. Lastly, some recent work on FinFETs is presented, along with the outstanding issues that people have been focusing on.
Introduction
As devices shrink further and further, the problems with conventional (planar) MOSFETs are increasing. Industry is currently at the 90nm node (ie. DRAM half metal pitch, which corresponds to gate lengths of about 70nm). As we go down to the 65nm, 45nm, etc nodes, there seem to be no viable options of continuing forth with the conventional MOSFET. Severe short channel effects (SCE) such as VT rolloff and drain induced barrier lowering (DIBL), increasing leakage currents such as subthreshold S/D leakage, D/B (GIDL), gate direct tunneling leakage, and hot carrier effects that result in device degradation is plaguing the industry (at the device level; there are other BEOL (back-end of the line) problems such as interconnect RC delays which we won’t discuss here). Reducing the power supply Vdd helps reduce power and hot carrier effects, but worsens performance. Performance can be improved back by lowering VT but at the cost of worsening S/D leakage. To reduce DIBL and increase adequate channel control by the gate, the oxide thickness can be reduced, but that increases gate leakage. Solving one problem leads to another. Efforts are on to find a suitable high-k gate dielectric so that a thicker physical oxide can be used to help reduce gate leakage and yet have adequate channel control, but this search has not been successful to the point of being usable. There are problems with band alignment (w.r.t Si) and/or thermal instability problems and/or interface states problems (with Si). The thermal instability problem has led researchers to search for metal gate electrodes instead of polysilicon (because insufficient activation leads to poly depletion effects). But metal gates with suitable work functions haven’t been found to the point of being usable. In the absence of this, polysilicon continues to be used, whose work function demands that VT be set by high channel doping. High channel doping in turn leads to random dopant fluctuations (at small gate lengths) as well as increased impurity scattering and therefore reduced mobility. Indeed, it is felt that instead of planar MOSFETs, a double gate device will be needed at gate lengths below 50nm [1] in order to be able to continue forth on the shrinking path.
What is a DG-MOSFET?
Double gate MOSFETs (DG-FET) is a MOSFET that has two gates to control the channel. Its schematic Its main advantage is that of improved gate-channel control. In conjunction with ultra thin bodies in an SOI implementation (FDSOI DG-FET), it additionally offers reduced SCE, because all of the drain field lines are not able to reach the source. This is because the gate oxide has a lower dielectric constant than Si (assuming the oxide is SiO2), and also because the body is ultra thin. Because of its greater resilience to SCE and greater gate-channel control, the physical gate thickness can be increased (compared to planar MOSFET). Thus it also brings along reduced leakage currents (gate leakage as well as S/D leakage).
There are 2 kinds of DG-FETs:
• Symmetric
• Asymmetric
Symmetric DG-FETs have identical gate electrode materials for the front and back gates (ie. top and bottom gates). When symmetrically driven, the channel is formed at both the surfaces. In an asymmetric DG-FET, the top and bottom gate electrode materials can differ (eg. n+ poly and p+ poly). When symmetrically driven this would end up forming a channel on only one of the surfaces. Both have their advantages and disadvantages. Recent work regarding them will be described in a later section in this report.
Energy band diagrams for symmetrical and asymmetrical DG-FETs The biggest and perhaps the only stumbling block with DG-FETs is its fabrication. One can conceive of 3 ways [4, 7] to fabricate a DG-FET, labeled
What is a FinFET?
Type 3 DG-FETs are called FinFETs. Even though current conduction is in the plane of the wafer, it is not strictly a planar device. Rather, it is referred to as a quasi-planar device, because its geometry in the vertical direction (viz. the fin height) also affects device behavior. Amongst the DG-FET types, the FinFET is the easiest one to fabricate. Its schematic Because of the vertically thin channel structure, it is referred to as a fin because it resembles a fish’s fin; hence the name FinFET. A gate can also be fabricated at the top of the fin, in which case it is a triple gate FET. Or optionally, the oxide above the fin can be made thick enough so that the gate above the fin is as good as not being present. (This helps in reducing corner effects, discussed later in this report)
It should be noted that while the gate length L of a FinFET is in the same sense as that in a conventional planar FET, the device width W is quite different. W is defined as:
where Hfin and Tfin are the fin height and thickness respectively (see Fig. 4 above. Some literature refers to the fin thickness as the fin width). The reason for this is quite clear when one notices that W as defined above is indeed the width of the gate region that is in touch with (ie. in control of) the channel in the fin (albeit with a dielectric in between). This fact can especially be seen if one unfolds the gate (ie. unwraps it).
The above definition of device width is for a triple gate FinFET. If the gate above the fin is absent/ineffective, then the Tfin term in the above definition is taken out.
On the surface, this freedom in the vertical direction (of increasing Hfin) is a much desired capability since it lets one increase the device width W without increasing the planar layout area! (Increasing W increases the Ion, a desirable feature). However, it will be seen in subsequent sections in this report, that there is a definite range (in relation to Tfin) beyond which Hfin should not be increased, else one encounters