fault detection in VLSI circuit

Test-Generation-Based Fault Detection in
Analog VLSI Circuits Using Neural Networks
Here, a novel test methodology for
the detection of catastrophic and parametric faults present
in analog very large scale integration circuits is described.

Introduction:
Testing of analog very large scale integration (VLSI) circuits is a challenge in itself. The high analog test cost results from many factors, such as

expensive test equipment, long test development time, and long

test production time.An effective test methodology is a
very important issue in the production of an IC and has direct
consequences on the price and the quality of the final product.


Faults in Analog Circuits:
Faults present in ICs can be divided into three classes:

1)permanent faults, which are faults in existence long enough to

be observed at test time;
2) temporary fault, which appear and disappear in short intervals of

time;
3) delay faults, which affect the operating speed of the
circuit.

Test pattern Generation.
The test pattern generator

must find an optimal set of test stimuli which detects all

modeled faults in the VLSI circuit. Thus the problem of test signal generation is

an optimization problem in principle. artificial intelligence methods have gained

much attention for Test vector generation
. Genetic algorithms have proven to be

effective in VLSI applications, including circuit layout and

partitioning, cell placement, routing, and automatic test

generation. a genetic algorithm is used as a test pattern

generatorto generate a piece-wise linear (PWL)

stimulus.

PWL Signal Generation:
all faults can be made visible in the measurement space By exciting the CUT with pulses and ramps whose
frequency spectrum stretches over a wide range of frequencies,
a transient PWL signal is generated for detection of both
catastrophic and parametric faults present in the circuits.


Feature Extraction Using Wavelets
Wavelet transform (WT) is capable of providing the time and
frequency resolution simultaneously and hence giving time-
frequency representation of the signal.
The output voltage response of the signal is captured and is
sampled with the sampling frequency of 5f, where f is the basic
frequency of the signal. When this signal passes through the
filter bank, the multiresolution decomposition of the signal
takes place.

Proposed Fault Detection Method Using PWL
Signal
Fault Detection Using Neural Networks:
Artificial intelligence techniques are popularly used in many
VLSI problems. In many studies neural networks are used in
fault detection and classification problems
a probabilistic neural
network (PNN) is used for the detection of catastrophic faults,
but AC current, AC voltage, DC current, and DC voltage are
the four measurements used for training the neural network.
a back propagation neural (BPN) net and a self organizing map
are used for fault classification

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