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In this paper fast pipelined digit-serial/parallel multipliers are
proposed. The conventional digit-serial/parallel multipliers and
their pipelined versions are presented. Every structure has been
implemented on FPGA and the results are given. These results
have been analysed and it is detected that the pipelined ones do
not have the throughput improvement expected because of a
logic depth increment. As a consequence, a new structure
based on the fast serial/parallel multiplier proposed in [1] has
been developed. The new multipliers designed achieve better
performance than the previous ones: their throughput is higher
than it in the pipelined serial/parallel multipliers with nearly
the same cost in area.
1. INTRODUCTION
Real-time signal processing hardware requires efficient
multiplier units. However, each application needs different
sample rates; from speech to image or radar a wide frequency
range is covered. In several cases, it is senseless to use a bitparallel
circuit: it has an important cost in area and runs faster
than the throughput required by the application. In these cases,
the bit-serial [2] or digit-serial approach became an important
alternative to efficiently implement custom DSP circuits.
Furthermore, in FPGA-targeted applications, the serial stream
of data matches better with the structure of such devices [3].
In digit-serial computation, data words of size W bits are
partitioned into digits of size N bits (the digit-size, N, is divisor
of the word-size, W) and are processed serially one digit at a
time with the least significant digit first. A complete word is
processed in P=W/N clock cycles and consecutive words
follow each other continuously. The time of P cycles is named
a sample period. In every digit-serial operator, it is necessary to
add some control signals to indicate, for example, a new word
entry. The digit-serial processors include parallel-serial and
serial-parallel converters to process in digit format and to
present the result in parallel one. The digit-serial operators are
cascaded following the data-flow algorithm in a pipeline
fashion. A detailed explanation of this kind of architectures can
be found in [4], [5], [6], [7], [8], [9]. A set of digit-serial
architectures can be designed by using different digit-sizes.
Each element of the family has a specific size and throughput.
Thus, it is possible to choose the digit-size that best suits the
speed of the application, minimising the cost in terms of area.
In this paper a set of fast pipelined serial/parallel multipliers
are proposed. All circuits compute the data-coefficient
multiplication in two’s complement representation. All the
topologies have been implemented on an EPF10K50GC403-3
Altera FPGA for W=8 bits size (data and coeficients) using the
default compilation options (automatic placement and routing).
This paper is organised in four parts: in Section 2 and 3 the
digit-serial/parallel multipliers and the pipelined digitserial/
parallel ones are respectively explained, and the results of
each one implementation on FPGA are given. In next section, a
brief discussion of those results is made. In Section 5, more
efficient pipelined digit-serial/parallel multipliers are proposed
and the results of their implementation on FPGA are also given.
Finally, the conclusions are presented.
2. SERIAL/PARALLEL MULTIPLIER
Serial/parallel multipliers use the shift-and-add algorithm to
compute the multiplication of a coefficient, which is given in
parallel form, by a data, which enters in the multiplier in serial
style. Assuming coefficient, C, with Wc bits, and data, X, with
Wd bits, are two’s complement numbers, the equation of the
serial/parallel multiplier can be written