Energy-Delay Estimation Technique for High-Performance Microprocessor VLSI Adders

Abstract
In this paper, we motivate the concept of comparing
VLSI adders based on their energy-delay trade-offs and
present a technique for estimating the energy-delay space
of various high-performance VLSI adder topologies.
Further, we show that our estimates accurately represent
tradeoffs in the energy-delay space for high-performance
32-bit and 64-bit processor adders in 0.13μm and 0.10μm
CMOS technologies, with an accuracy of 8% in delay
estimates and 20% in energy estimates, compared with
simulated data.
1. Introduction
In the course of VLSI processor design it is very
important to choose the adder topology that would yield
the desired performance. However, the performance of a
chosen topology will be known only after the design is
finished. Therefore a lingering question remains: could
we have achieved a higher performance, or could we have
had a better VLSI adder topology? The answers to those
questions are generally not known. There is no consistent
and realistic speed estimation method employed today by
the computer arithmetic community. Most of the
algorithms are based on out-dated methods of counting
the number of logic gates in the critical path producing
inaccurate and misleading results. The importance of
loading and wire delay is not taken into account by most.
Knowles has shown how different topologies may
influence fan-out and wiring density thus influencing
design decisions and yielding better area/power than
known cases [1]. This work has further emphasized a
disconnect existing between algorithms that are used to
derive VLSI adder topologies and the final result. In
previous work we have shown the importance of
accounting for fan-in and fan-out on the critical path, not
merely the number of logic levels [2]. This has led to the
method of Logical Effort (LE) [3], which has been
popularized by Harris [4]. Recently, we used Logical
Effort to estimate the speed of various VLSI adders and
we compared those results with those obtained using a
more complex circuit simulation tool H-SPICE [5]. This
comparison showed a good match and pointed to the right
direction. However, the process of analysis was now time
consuming and did not provide a comparison for various
circuit sizing that could have been applied. This paper is
organized as follows: the second section discusses speed
estimation using more realistic measures such as logical
effort, the third section introduces the energy effects and
discusses the performance in the energy-delay space, the
fourth section describes the estimation tool that was
developed, the fifth section shows results applied to
several well known adder topologies and compares them
with simulated results in 0.13μm technology.
2. Speed Estimation
The speed of a VLSI adder depends on many factors:
the technology of implementation (and its own internal
rules), circuit family used for the implementation, sizing
of transistors, chosen topology of the VLSI adder, and
many other second order effect parameters. There were no
simple rules that could be applied when estimating VLSI
adder speed. Skilled engineers are capable of fine-tuning
the design by carefully selecting transistor sizes, obtaining
the best performance and energy trade-off. Therefore it is
very difficult, if not impossible, to predict which of the
topologies developed by the computer arithmetic
community is best, even if it is really useful.
2.1 Logical Effort
Logical Effort methodology takes into account the
fact that the speed of a digital circuit block is dependent
on its output load (fan-out) and its topology (fan-in).
Further, LE introduces technology independence by
normalizing the speed to that of a minimal size inverter
This work has been supported by SRC Research Grant
No. 931.001 and California MICRO 01-063
Proceedings of the 16th IEEE Symposium on Computer Arithmetic (ARITH'03)
1063-6889/03 $17.00 © 2003 IEEE
which makes the comparisons of different topologies,
implemented in different technologies, possible. For
proper understanding and further reading of this paper the
reader should be familiar with the LE methodology [3,4].
We will briefly describe some of the main features of LE
in this sub-section. The delay expression of a logic block
in LE is given as:
d = f + p (1)
where p = parasitic delay, f = effort or stage delay.
Further f = gh where g is defined as logical effort and h
as electrical effort. Thus:
d = gh + p (2)
This dependency is illustrated in Fig. 1.
Fig. 1. Delay expressed in terms of a minimal size inverter
[3,4]
An important result of LE is that it provides a way of
determining appropriate transistor sizing of the critical
path to minimize delay. LE also provides an estimate of
the critical path delay. Logical Effort results are
summarized in Table 1.
Logical Effort tells us that the delay will be minimal when
each stage bears equal effort given as:
N
i i f g h F
1
ˆ = = (3)
In such a case, delay of the path will be equal to:
D = Nfˆ + P (4)
In order to calculate optimal transistor sizes to achieve
minimal delay, we start from the output and calculate Cin
for each stage, which determines the sizing of each stage.