29-10-2010, 08:52 AM
DYNAMIC MEMORY ACCESS MANAGEMENT FOR HIGH PERFORMANCE DSP APPLICATIONS USING HIGH-LEVEL SYNTHESIS
PRESENTED BY:NIRMAL JOSEPH
S7 ECE
College Of Engineering, Trivandrum
2007-11 batch
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OUTLINE
INTRODUCTION.
TARGETTED ARCHITECTURE.
HIGH LEVEL SYNTHESIS.
DESIGN FLOW.
CONCLUSION.
REFERENCES.
DYNAMIC MEMORY ACCESS(DMA)
Also called indeterminate access sequence.
A part of data is not known before the execution of the application.
Memory accesses are computed during the execution of application.
Example, the access sequence
S={A,C,B,X[1],X[i],X[j]……..}
HIGH PERFORMANCE DSP APPLICATIONS
Characterized by a large number of data accesses.
The entire memory access sequences are not known a priori.
Memory access is the limiting factor for the computational speed of DSP processors.
Example: video and image processing applications.
WHY DMA IS USING FOR HIGH PERFORMANCE DSP APPLICATIONS
Memory addresses of all data sequences can be calculated during the execution.
Time delay for memory access will get reduced.
Computational speed of DSP processors will get improved.
More efficient data handling and processing can be possible.
HOW DMA CAN BE IMPLEMENTED?
By developing efficient data path and memory architectures.
Generally two methods are used.
1.Memory architecture developed before data path architecture.
2.Data path architecture developed before memory architecture.
New architecture should satisfy parallel accesses without producing data access conflicts.
TARGETTED CIRCUIT ARCHITECTURE
Targets custom DSPs dedicated to computation intensive applications.
Targeted architecture composed of three distinct units.
1.Processing unit – contains data path& controller.
2.Memory unit -manages pipeline access to memories.
3.Communication unit- sends & receives data to and from the rest of system.
TARGETTED ARCHITECTURE
DYNAMIC ADDRESS SEQUENCER ARCHITECTURE
It is assumed that all dynamic addresses are calculated in the data path unit.
This sequencer architecture allows DMA.
The sequencer architecture is limited to one dynamic access per clock cycle.
Proposed sequencer contains four different units.
PARTS OF SEQUENCER ARCHITECTURE
1.Memory access scheduler.
2.Dynamic address controller.
3.Address generator.
4.Address translation table.
MEMORY ACCESS SCHEDULER
Knows the memory access sequence.
Controls the crossbar connecting data path access buses and memory.
Controls address generation progress in a synchronous manner.
Results in dynamic memory access.
ADDRESS CONTROLLER AND GENERATOR
Controller steers correct command signals and physical address to the right memory bank.
Address generator generates the corresponding memory addresses for DMA.
ADDRESS TRANSLATION TABLE
Every dynamic address access should go through the address translation table.
Translates logical address of the data to a data set.
HIGH LEVEL SYNTHESIS
A synthesis method to develop the proposed architecture.
Analogous to software compilation transposed to hardware domain.
Source specification is written in a high level language like MATLAB,C etc..
It is a constraint based design flow.
Contd…
HLS tools generate a Register Transfer Level(RTL) architecture.
RTL architecture respects both designer and system constraints.
Hardware resources are selected from technology specific libraries.
HLS synthesis tools, eg: GAUT,SPARK..etc.
HLS DESIGN FLOW
EXTENDED DATA FLOW GRAPH
Handles the constraints to be considered for the synthesis process.
Represents computations, control and data structures in a data flow fashion.
Capable of handling the new sequencer architectures.
MODELLING USING EDF GRAPH
SYNTHESIS PROCESS
GAUT-HLS tool is used for synthesis of the application.
Synthesis process contains two steps.
1.Operator selection and allocation.
2.Scheduling and binding.
OPERATOR SELECTION AND ALLOCATION
Selection and allocation of hardware resources.
HLS tool counts no. of resources required to execute the application.
Memory sequencer allocation based on parallel computations for operator allocation.
Enables parallelism of memory accesses.
SCHEDULING AND BINDING
A scheduling algorithm is generated based on EDF graph.
Memory unit operations are scheduled at the same time as processing unit operations.
Both memory sequencer and processing unit synthesis are considered in one scheduling and binding step.
HLS FOR A SINGLE SYNTHESIS STEP
CONCLUSION
A synthesis design flow based on a new sequencer architecture is proposed.
Proposed methodology allows DMA for DSP applications.
Reduces the address transfers between memory and data path units.
Fast processing of signals can be possible.
REFERENCES
J. Seo, T. Kim, and P. Panda, “Memory allocation and mapping in highlevelsynthesis: An integrated approach,” IEEE Trans. Very Large ScaleIntegr. (VLSI) Syst., vol. 11, no. 5, pp. 928–938, May 2003.
G. Corre, E. Senn, N. Julien, and E. Martin, “A memory aware behavioralsynthesis tool for real-time vlsi circuits,” in Proc. 14th ACMGreatLakes Symp. VLSI (GLSVLSI), New York, NY, 2004.
B. Le Gal, E.Casseu, and S.Huet “Dynamic memory access management for high performance dsp applications”,IEEE Trans. Very Large ScaleIntegr. (VLSI) Syst., vol. 16, no. 11, pp. 968–993, November 2008.
