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Dynamic Logic Circuits

abstract

Dynamic logic is temporary (transient) in that output levels will remain valid only for a certain period of time
Static logic retains its output level as long as power is applied
Dynamic logic is normally done with charging and selectively discharging capacitance (i.e. capacitive circuit nodes)
Precharge clock to charge the capacitance
Evaluate clock to discharge the capacitance depending on condition of logic inputs
Advantages over static logic:
Avoids duplicating logic twice as both N-tree and P-tree, as in standard CMOS
Typically can be used in very high performance applications
Very simple sequential memory circuits; amenable to synchronous logic
High density achievable
Consumes less power (in some cases)
Disadvantages compared to static logic:
Problems with clock synchronization and timing
Design is more difficult