disadvantages of finfet
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Hi i am hazirah i would like to get details on disadvantages of finfet .
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#2

The finFET is a transistor design, developed by Chenming Hu and colleagues at the University of California at Berkeley, which attempts to overcome the worst types of short-channel effects encountered by deep submicron transistors, such as the reduction of sweep induced by Drainage system (DIBL). These effects make it more difficult for the voltage at a gate electrode to deplete the channel below and stop the flow of carriers through the channel, ie, to turn off the transistor. By raising the channel on the surface of the wafer instead of creating the channel just below the surface, it is possible to wrap the door around three sides, providing a much greater electrostatic control over the carriers within it.


There are a number of subtly different forms of trigate transistor structure that are described as finFETs. The architecture typically takes advantage of self-aligned process steps to produce extremely narrow characteristics that are much smaller than the wavelength of light generally used for patterning devices on a silicon wafer. It is possible to create very thin fins - 20nm wide or less - on the surface of a silicon wafer using selective etching processes, although typically less than 20nm to 30nm can not be done currently due to lithographic resolution limits. The flap is used to form the raised channel. The door is then deposited so that it is wrapped around the flap to form the trigged structure. As the channel is extremely thin, the gate has much greater control over the carriers within it, but, when the device is on, the shape limits the current through it to a low level. Thus, multiple fins are used in parallel to provide greater resistance to the unit.

Originally, finFET was developed for use in silicon wafer over insulation (SOI). Recent developments have made it possible to produce finFETs working on mass silicon wafers and improve the performance of certain parameters. The sheer dopant profile used to control leakage in the bulk substrate has a beneficial impact on DIBL, although increased doping has a negative impact on variability. Completely depleted SOI (Guide) transistors have been shown to provide comparable or better performance than finFETs. However, the relative compatibility of the finFET silicon mass with the existing wafer manufacturing processes and today's wafer supply chain favors the finFET for the production of high volume IC at 22 nm and less. FinFETs have key advantages over planar bulk devices. They present more drive current per unit area than planar devices, largely because the height of the fin can be used to create a channel with a higher effective volume, but still take advantage of a wraparound door. The additional performance capability of the FinFETs can be used to obtain higher frequency numbers compared to the volume for a given power budget or a lower power. Power reduction can come from two sources: reduced need for wide standard and high capacity cells; And the ability to operate with a lower supply voltage for a given amount of leakage.
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