28-04-2011, 08:07 PM
1. A Fast VLSI Design Of Sms4 Cipher Based On Twisted BDDS-Box Architecture.
2. Left To Right Serial Multiplier For Large Number On FPGA.
3. A Compact AES Encryption Core On Xilinx FPGA.
4. An Improved RC6 Algorithm With The Same Structure Or Encryption And Decryption.
5. A Novel Multiplexer Based Truncated Array Multiplier.
A Generalization Of A Fast RNS Conversion For A New 4-Modulus Base.
