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PROJECT SPECIFICATION
Project Specification as I got on 1st Day
The LISA system integration group couples the automatically generated LISA processor simulators to various co simulation environments.
The existing LISA Bus Interface class hierarchy has to be extended with interfaces to communicate to different environments and on different levels of abstraction.
Initial Study
LISA 2.0 Language Tutorial
Processor: “QSIP” Architecture
Tools: CoWare LISATek EDGE Processor Designer
(LDesigner, LISA Compiler, generated Tool Suites)
HUB System Integrator:
Multiprocessor Debugger
Bus Interface: Simple memory adapter for the simple_bus
Synopsys Documentation
Tools: CoCentric SystemStudio
Libraries: DesignWare AMBA SystemC Library
Direct Interface
Direct Interface
Does not require bus ownership
Simulation Time is not advanced
Used to implement debugging features for masters or to initialize slaves
Involves Parameters
Address
Data Buffer
Total no. of Bytes
Blocking and Non Blocking Interface
Blocking and Non Blocking Interface
Common features:
Address Decoding
Bus access request
Parameters
Blocking and Non Blocking Interface
Challenges
Not a simple 1:1 conversion of APIs:
Adaption: LISA word size ↔ AMBA databus width
Enhanced features only on LISA side:
flexible subblock access mechanism
flexible word alignment
Enhanced features only on AMBA side:
wrap/increment mode
split transaction
Problems
An example System
Monitor Attached to AHB Bus
Memory as seen by processor
Time didnt permit
Implement the adapter for gnu 3.x version in upgraded environment (2003.03)
Test the case: amba_data_width < lisa_word_siz
Develop a direct adapter for the related APB Bus
APIs for different environments
IP Creation Flows
Bouquets & Brickbats