PRESENTED BY:
B.Vinod kumar
Z.Vijay kumar
C.V. Karunakar reddy
M.Sreeja
G.Ramesh

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objective
In present CMOS circuits the power dissipation caused by leakage current cannot be neglected as the technology scaling down
Here single treshold transmission gate D flip flop is the bench circuit and new transmission gate flip flop based on different techniques are used
Here the techniques like dual threshold and the stacking of MTCMOS transistors is used to reduce the leakage current.
The values power, delay , area are compared with the bench circuit in deep sub micron technology
As the technology scaling down
• Leakage power comes into consideration
• area of the circuit decreases
• Delay of the circuit decreases
Components of Power
• Dynamic
– Signal transitions
• Glitches
– Short-circuit
• Static
– Leakage
• Power of a Transition: Ptran
Dynamic Power
• Depends on the switching activity of the gate and the load capacitance at the output node (switching capacitance).
• Supply Voltage and clock frequency.
• Dynamic power = Σ 0.5 αi fclk CLi VDD2
All gates i
where fclk clock frequency
αi activity factor of gate i
CLi load capacitance of gate i
• Short Circuit Power of a Transition: Psc
• Leakage power
• Majority of leakage dissipation is due to sub threshold leakage current.