Design of Hybrid Encoded Booth Multiplier with Reduced Switching Activity Technique
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Abstract-
This paper explores the design approach of a low
power Hybrid Encoded Booth Multiplier (HEBM) with Reduced
Switching Activity Technique (RSAT) and low power 0.13μm
adder for DSP functions that encounter a wide diversity of
operating scenarios in battery powered low power wireless sensor
network system. This RSAT approach has been applied on the
hybrid encoder of the multiplier to reduce the power
consumption. The hybrid encoder in the low power multiplier
uses both the Booth and proposed technique. If the number of 1’s
less than or equal to three the proposed encoding technique used
otherwise go for Booth technique. The proposed adder cell used
in the multiplier block consumes less power than the other
previous adder techniques. The switching activity of the proposed
multiplier has been reduced by 86% and 46% compared with
conventional and Booth multiplier respectively. It is observed
from the device level simulation using TANNER 12.6 EDA that
the power consumption of the proposed multiplier has been
reduced by 87% and 26% compared with conventional and
Booth multiplier.
Keywords-low power, Hybrid Encoded Booth Multiplier,
RSAT, wireless sensor node.
I. INTRODUCTION
Wireless sensor networks are composed of a set of
autonomous microsystems scattered in a specific
environment. Each node monitors physical quantities of its
close environment and the measured data are stored and then
sent through the self organized network to a base station.
Main applications of these sensor networks are monitoring of
environmental physical quantities such as temperature,
humidity or vibrations in different places such as buildings,
industries or automotive environments. Low power and low
energy VLSI circuits have become an important issue in
today's consumer electronics.
The number of embedded devices that must run with
battery power or parasitic power are increased. The traditional
approaches for designing these systems vary according to the
need of low power design. Improving the performance and
reduce the power consumption of the circuit designs are
having the challenges in low power VLSI Design. The energy
efficient Digital Signal Processing (DSP) modules are
becoming necessary in wireless sensor networks, in which tens
to thousands of battery operated micro sensor nodes are
deployed remotely and used to relay sensing data to the end
user [1-4]. The DSP functions mostly make use of the Multiply
and Accumulate (MAC) operation in which the multiplication
function is the most power consuming task. It is essential to
implement the power-efficient multipliers for low power DSP
modules. The development of multiplier with short critical path
and low power consumption has become the important area of
investigation. The inclusion of multiplying capabilities to
processor architecture can provide increase in performance for
low power wireless multimedia and DSP applications. These
DSP applications may be Fourier Transform (FFT), Discrete
Cosine Transform (DCT), quantization, or neural networks. It
is well known that the clamp down approach of dynamic
power which is the major part of total power dissipation
may provide significant reduction in power consumption. This
can be achieved by minimizing the transition capacitance.
The reduction of dynamic power consumption by
minimizing the switched capacitance has been reported by
many researchers [5-11]. Choi et al [5] proposed Partially
Guarded Computation (PGC) which divides the arithmetic
units such as adders and multipliers into two parts, and freeze
the unused part to minimize the power consumption. The
reported results show that the PGC can reduce power
consumption by 10% to 44% in an array multiplier with 30%
to 36% area overhead in speech related applications.
A 32-bit 2’s complement adder equipping a Dynamic-
Range Determination (DRD) unit and a sign-extension unit
was reported by Chen et al [6]. This design tends to reduce
the power dissipation of conventional adders for multimedia
applications. Chen et al [7] presented a multiplier using the
DRD unit to select the input operand with a smaller effective
dynamic range to yield the Booth codes and it saves 30%
power dissipation than conventional ones. Benini et al [8]
reported that, the technique for glitching power minimization
by replacing some existing gates with functionally equivalent
one. This saves 6.3% of total power dissipation since it
operates in the layout level environment

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