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1. INTRODUCTION TO VHDL
1.1 OVERVIEW
VHDL is an industry standard language for the description, modelling and synthesis of digital circuits and systems. It arose out of the US government’s Very High Speed Integrated Circuits (VHISC) program. On the course of this program, it became clear that there was a need of a standard language for describing the structure, and function of integrated circuits (IC). Hence the VHSIC Hardware Description Language (VHDL) was developed. It was subsequently developed further under the auspices of the institute of Electrical and Electronics Engineers (IEEE) and adopted in the form of the IEEE standard 1076 standard HDL language reference manual in 1987.
VHDL is particularly well suited for designing with programmable logic devices. Designing with large capacity CPLDs and FPGAs of 500 to more than 100,000 gates, engineers can no longer use Boolean equations or gate level descriptions to quickly and efficiently complete a design. VHDL provides high level language constructs that enable designers to describe large circuits and being products to market rapidly. It supports creation of libraries in which to store components for reuse in subsequent designs. Because it is a standard language, it provides probability of code between synthesis and simulation tools, as well as device independent design. It also facilitates converting a design from a programmable logic to an ASIC implementation.
VHDL enables the description of a digital design ad different levels of abstractions such as logarithmic register transfer and logic gate level. A user can abstract a design or hide the implementation details of a design using VHDL. In a top-down design methodology, a designer usually represents the system in high-level abstraction first and latter convert it to a more detailed design.
A design description written in VHDL is usually run through a VHDL simulator to verify the behaviours of a modelled system. To simulate a design, the designer must be supplied the simulator with a set of stimuli. The simulation program applies the stimuli to the input description specified times and generates the responses of the circuit. The waveforms, timing diagrams or tabular listings may illustrate the result of the simulation program. The designer interprets these results to verify whether or not the designs are satisfactory. A simulator can be used at any stages of a design process.
At a higher level of design process, simulation provides information regarding the functionality of the system under the design. Normally, the simulation of this level is very quick, but doesn’t provide the detailed information about the circuit’s functionality and timing. As design process, goes down to the lower level, the simulation will take longer time. The simulation of the lower level of the design process, runs more slowly, but provides more detailed information about the timing and functionality of the circuits. VHDL allows mixed level design in which some of the modules are describe in a high level of abstraction and some in a lower level of abstraction. The advantage mixed level simulation is that designer can focus on the design of the timing critical modules, while leaving the non-critical modules to a later stage. To avoid the higher cost of low level simulation runs, simulator should be used to detect the design flow as early as possible.
1.2 HARDWARE ABSTRACTION
VHDL is used to describe a model for a digital hardware device. This model specifies the external view of the device and one or more internal views. The internal view of the device specifies the functionality or structure, while the external view specifies the interface of the device through which it communicates with the other models in its environment. Figure I.I shows the hardware device and the corresponding software model.
The device to device model mapping is strictly a one to many. That is, a hardware device may have many device models as shown infig4.2b. Even though entities 1 through N represent N different entities from the VHDL point of view, in reality they represent the same hardware device.
1.3 BASIC TERMINOLOGY
The building blocks of VHDL language along with some common terms are given below:
• Entity: All designs are expressed in terms of entities .An entity is the most basic building block in a design. The upppermost level of the is the top level entity.If the design is hierarchical then the top level description will have lower level descriptions containing it. These lower level descriptions will be lower level entities containing ht etop level entity description.
• Architecture: All entities that can be simulated have an architecture description. Architecture describes the behaviour of the entities. A single entity can have multiple architectures. One architecture might be behavioural, while another may be structural description of the design.
• Package: Package is a collection of commonly used data types and subprograms used in a design.
• Process: Process is the basic unit of execution in VHDL. All operations that are performed in a simulation of a VHDL description are broken into single or multiple processes.
1.3.1 ENTITY DECLARATION
A VHDL entityspecifies the name of the entity,the ports of the entityand entity related information.All designs arecreatedusing one or more entities.The entity describes the interface to the VHDL model. The syntax for an entity declaration is :
entity entity_name is
[generic (list_of_generics_and_their_types;]
[port(list_of_interface_port_names_and_their_types);]
[entity_item_declarations]
[begin
entity_statements]
end[entity][entity_name];
1.3.2 ARCHITECTURE BODY
The architecture body describes the internal view of an entity. It describes the functionality or the structure of the entity. The syntax of an architecture body is:
architecture architecture_name of entity_name is
[architecture_item_declarations]
begin
concurrent_statements—these are
process_statement
block_statement
concurrent_procedure_call_statement
concurrent_assertion_statement
concurrent_signal_assignment_statements
component_instantiation_statement
generate_statement
end [architecture] [architecture_name];
1.3.3 PROCESS STATEMENT
The process statement contains sequential statements that describe the functionality of a portion of an entity in sequential terms.
The syntax of process statement is:
[process _label:] process [(sensitivity_list)] [is]
[process_item_declarations]
begin
sequential_ statement
variable_assignment _ statement
signal_assignment_ statement
wait_ statement
if statement
case statement
loop statement
null statement
exit statement
next statement
assertion statement
report statement
procedure call statement
return statement
end process [process label];
A set of signals to which the process is sensitive is defined by the sensitivity list. The processs then suspends after executing the last sequential statement and wait for another event to occur on a signal in the sensitivity list. Items declared in the item declaration part are available for use only within the process.
1.3.4 COMPONENT DECLARATION
An architecture body can also make use of other entities described separately and placed in design libraries. In order to do this, the architecture must declare a component which can be thought of as a template defining a virtual design entity, to be instantiated within the architecture.Later, a configuration, specification can be used to specify matching library entity to use. The syntax of a component declaration is:
component identifier
[ local_generic_clause]
[ local_port_clause]
end component;
1.3.5 COMPONENT INSTANTIATION
A component defined in architecture may be instantiated using the syntax:
instantiation_label:
component_name
[generic_map_aspect]
[port_map_aspect];
This indicates that the architecture contains an instance of the named component, with actual values specified for generic constants, and with the component ports connected to actual signals or entity ports
1.3.6 PACKAGE DECLARATION
A package is a collection of types, constants, subprograms and possibly other things, usually intended to implement some particular service or to isolate a group of related items. In particular the details of constant values and subprogram bodies can be hidden from users of package, with only their interfaces made visible. A package may be split into 2 parts: a package declaration, which defines its interface and a package body which defines the deferred details. The body part may be omitted if there are no deferred details.
The declarations define things which are to be visible to users of the package, and which are allows visible inside the package body. A package declaration contains a set of declarations that may possibly be shared by many design units. It defines the interface to the package; it defines items that can be made visible to other design units. A package body in contrast contains the hidden details of a package. The syntax of a package declaration is:
package package¬_name is
package_item_declaration—these may be
subprogram declarations
type declarations
subtype declarations
constant declarations
signal declarations
variable declarations
file declarations
alias declarations
component declarations
attribute declarations
attribute specifications
disconnection specifications
use clauses
end [package][ package_name];
1.3.7 VARIABLE ASSIGNMENT STATEMENT
Variables can be declared and used inside a process statement. A variable is assigned a value using the variable assignment statement that typically has the form
variable-object := expression;
The expression is evaluated when the statement is executed and the computed value is assigned to the variable object instantaneously, that is, at the current simulation time.
1.3.8 SIGNAL ASSIGNMENT STATEMENT
Signals are assigned values using a signal assignment statement The simplest form of a signal assignment statement is
signal-object <= expression [ after delay-value ];
A signal assignment statement can appear within a process or outside of a process. If it occurs outside of a process, it is considered to be a concurrent signal assignment statement. This' is discussed in the next chapter. When a signal assignment statement appears within a process, it is considered to be a sequential signal assignment statement and is executed in sequence with respect to the other sequential statements that appear within that process.