I want to make an scientific calculator using vhdl please help me.

FPGA (Field Programmable Gate Array) is one of the most powerful and successful tools for the development of real time systems. It is also one of the most widely used. A calculator is an example of such a real time system. This project aims to design a simple calculator using FPGA. The calculator would be able to perform basic calculations such as addition, subtraction, multiplication and division. The system was designed using VHDL (Very high speed integrated circuit Hardware Description Language). The target board used was a Xilinx Spartan 3A series, the VHDL codes were targeted to the board using Xilinx ISE. A numeric keypad was used as the input device and the onboard LCD of the target board was used as the output device. The whole system design was divided into 3 phases.

Introduction

The purpose of this lab is to implement a finite state machine in VHDL to perform three simple calculations: addition, subtraction, and multiplication. You are required to design a calculator using VHDL. It should take in 3 inputs: two 4-bit operands and a 2-bit operator. Check it's functionality using ALDEC VHDL simulator, then wire up the DIP switch to the XS40 board and download your program unto XS40 board and verify correctness again.

Apparatus Required:

10 pin DIP Switch
XS40 Board


Program:


--
-- Tony Givargis
--

--********************************************************************

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;

--********************************************************************

entity WRLED is
port (rst: in STD_LOGIC;
clk: in STD_LOGIC;
val : in UNSIGNED(3 downto 0);
led: out UNSIGNED(6 downto 0));
end WRLED;

--********************************************************************

architecture WRLED_arch of WRLED is

-- finish entity

end WRLED_arch;

--********************************************************************

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;

--********************************************************************

entity XS40 is
port (rst: in STD_LOGIC;
clk: in STD_LOGIC;

--define operands and operator here

led: out UNSIGNED(6 downto 0));
end XS40;

--********************************************************************

architecture XS40_ARCH of XS40 is

component WRLED
port(val: in UNSIGNED(3 downto 0);
led: out UNSIGNED(6 downto 0));
end component;

signal val:UNSIGNED(3 downto 0);

begin

U1:WRLED port map(val, led);

process(rst, clk, ...)

-- insert calculator code here

end process;
end XS40_ARCH;

I. Procedure

simulation:

Complete the code and test the functionality using ALDEC VHDL.
You may find the 7-segment display diagram useful to complete the WRLED entity.
Show TA the waveforms.
downloading:
If you are unfamiliar with downloading to the XS40 board, run through the tutorial and see if you can get the XS40 board to count.
(Remember: Jumper on J4 needs to be set when loading program but disconnected when running program)
Wire up the circuit, it is up to you to choose the connections. You will probably need the circuit diagram or the XS40 board manual.
You will need to create a .ucf to download your VHDL calculator.
Generate a bit file and download your program unto the XS40 board and test your program.