Abstract
Modern FPGA chips, with their larger memorycapacity and reconfigurability potential, are opening newfrontiers in rapid prototyping of embedded systems. Withthe advent of high density FPGAs it is now possible toimplement a high performance VLIW processor core in anFPGA. Architecture based on Very Long Instruction Word(VLIW) processors are an optimal choice in the attempt toobtain high performance level in embedded system. In VLIWarchitecture ,the effectiveness of these processors dependson the ability of compilers to provide sufficient instructionlevel parallelism(ILP) in program code. Using advancedcompiler technology could take these functions, This paperdescribes research result about enabling the DSP TMS320C6201 model that be described with machine descriptionlanguage (MDES) in compiler technology for imageprocessing applications by exploiting FPGA technology andassembly code that be more known as Lcode would begenerated by the compiler depends on MDES given whenrunning the compiler. We present a DSP C6201 VHDLfrom MDES definition with VLIW architecture model usingcompiler technology. We call this new development asModified Minimum Mandatory Modules (M4) approach thatbe derived from M3 methodology. Our goals are to keep theflexibility of DSP in order to shorten the development cycle.Our results demonstrate that an algorithm can easily, in anoptimal manner, specified and then converted to VHDLlanguage and implemented on an FPGA device with systemlevel software. This makes our approach suitable fordeveloping co-design environments. Our approach appliessome criteria for co-design tools : flexibility modularity,performance, and reusability.
Keywords : Rapid Protoyping, MDES, TMS320C6201, LCode,FPGA
.I. INTRODUCTION
For the design of systems on chip (SoCs), the usage ofFPGAs is increasing more and more. In many situations,where normally an ASIC would have been designed, anFPGA design has more advantages. Designing for FPGAsbrings lower non-recurring engineering (NRE) costs thandesigning the same SoC for an ASIC. This is mainly causedby the fact that no external NRE costs have to be made, theIC itself is already manufactured. The manufacturingprocess of the IC is responsible for a large part of the costs.A mask set for an ASIC in the 90 nm process cost about$1M[4]. The FPGA (Field Programmable Gate Array), withits reconfigurability and easy integration capacity becomes akey solution for rapid prototyping of embedded system. Inthe standard FPGA base prototyping methodology,algorithms are first developed on a personal computer orworkstation in standard software programming languagessuch as C or Matlab. When the algorithm is laterimplemented in hardware, that code is translated into ahardware description language such as VHDL or Verilog.Finally, the design is synthesized for an FPGA-basedenvironment where it can be tested [5].II. CONCEPT OF MODULAR VLIW PROCESSORIn the following section, we introduce a short descriptionabout OpenIMPACT compiler, assembler code generatingin DSP TI model, andA. OpenIMPACT CompilerOpenIMPACT compiles the original source code into anassembly intermediate representation (IR) called Lcode.The Lcode produced is optimized for ILP, but not for aspecific machine. The compilation and simulation tools forthis evaluation were provided by the OpenIMPACTcompiler, produced by group of Wen-mei Hwu at theUniversity of Illinois [2]. The OpenIMPACT environmentincludes a trace-driven simulator and an ILP compiler. Thesimulator enables both statistical and cycle-accurate tracedrivensimulation of a variety of parameterizablearchitecture models, including both VLIW and in-ordersuperscalar datapaths. The Open IMPACT compilersupports many aggressive compiler optimizations includingprocedure inlining, loop unrolling, speculation, andpredication. IMPACT organizes its optimizations into threelevels: