28-04-2011, 08:11 PM
1. System Architecture And Implementation Of MIMO Sphere Decoders On FPGA.
2. Cost-Efficient SHA Hardware Accelerators.
3. Low-Power Leading-Zero Counting An Anticipation Logic For High-Speed Floating Point Unit.
4. Superscalar Power Efficient Fast Fourier Transform FFT Architecture
5. A New High-Speed Architecture For Reed-Solomon Decoder.
