Abstract
With the increased use of microprocessors in embedded applications, the need for smaller, more power efficient and cost effective processors has promoted research into improving these areas. Whilst submicron technologies are continually advancing, there are other areas which can be inspected for the improvement of performance.In embedded systems, where economic incentives to reduce both RAM and ROM are strong, the size of compiled code is increasingly important. Similarly, in mobile and network computing, the need to transmit an executable before running it places a premium on code size. Code compression is very effective technique to enhance the perfomance of on-chip systems.It reduce code size by taking advantage of instruction repetition. code compression increase available memory space. By compressing the program that later resides on the processor, and including only a small decompression unit to decompress instructions on-the-fly, the processing core can continue to operate without any change. Research has shown this sort of technique applied to single- issue (usually RISC) processors has the potential for not only program (and hence chip) size reduction, but also power savings and performance enhancement. The idea of using code compression as a tool for chip size reduction in microprocessors has mostly incited interest in the area of single instruction issue (usually RISC) processors.
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